Technical Note
4/13
www.rohm.com
2011.05 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD95830MUV
Block Diagram
Pin Configuration Pin Function
PIN
No.
PIN
Name
PIN Function
1,2,32 VIN1 Power Supply Voltage Input Pin for 1ch.
3 VINS
Power Supply Voltage Sense Pin.
Input Pin for V
REG.
4 VREG Reference Voltage Inside IC.
5 VCC 5V Power Supply Input Pin.
6,20 GND Sense GND.
7-9 VIN2 Power Supply Voltage Input Pin for 2ch.
10-12 PGND2 Power GND for 2ch.
13-15 SW2 High side FET Source Pin 2.
16 BOOT2 High side FET Gate Driver Power Supply Pin 2.
17 EN2
Enable Input Pin 2.
(00.3V:OFF, 2.215V:ON).
18 VOUT2 Output Voltage Sense / Discharge Pin 2.
19 FB2 Output Voltage Feedback Pin 2.
21 TEST Pin for TEST. Connect to GND.
22 FB1 Output Voltage Feedback Pin 1.
23 VOUT1 Output Voltage Sense / Discharge Pin 1.
24 EN1
Enable Input Pin 1.
(00.3V:OFF, 2.215V:ON).
25 BOOT1 High side FET Gate Driver Power Supply Pin 1.
26-28 SW1 High side FET Source Pin 1.
29-31 PGND1 Power GND for 1ch.
reverse FIN Exposed Pad, Connect to GND.
1
2
3
4
5 6 7
8
9
10
11
12
13
14
15
16
24 23 22
21
20 19 18
17
32
31
30
29
28
27
26
25
BOOT1
SW1
VIN1
V
IN1
V
INS
EN1
V
OUT1
FB1
TEST
GND
FB2
V
OUT2
EN2
BOOT2
SW2
SW2
PGND2
PGND2
PGND2
V
IN2
SW1
SW1
PGND1
PGND1
PGND1
V
IN1
GND
V
IN2
V
IN2
V
REG
VCC
SW2
Thermal
Protection
R
S
Q
TSD
Delay
H
3
Reg
TM
Controller
Block
VREG
GND
BOOT1
VIN1
SW1
PGND1
25
26
27
28
6, 20
Reference
Block
UVLO
EN2
BOOT2
VIN2
SW2
17
16
5VReg
VREG
4
3
OVP
OVP
Driver
Circuit
R
S
Q
H
3
Reg
TM
Controller
Block
UVLO
OCP2
SCP
TSD
Driver
Circuit
FB1
22
EN1
24
FB2
19
0.96
V
FB1
OVP1
0.96
V
FB2
VREG
VREG
VOUT2
EN1/UVLO
VOUT1
23
VOUT1
VOUT2
VOUT1
VIN
VOUT2
V
IN
18
VINS
VIN
EN1
VREG
UVLO
OCP1
SCP
TSD
+
-
0.56V
FB2
+
-
0.56V
FB1
SCP
EN2
VREG
SW1
OCP1
SW2
OCP2
+
-
+
-
OVP
OVP2
5
VCC
VINS
+
PGND2
Soft
Start
-
+
REF1
SS1
REF1
EN1
UVLO
SS1
Soft
Start
EN2
UVLO
SS2
EN2/UVLO
+
-
+
REF2
SS2
VREG
13
14
15
10
11
12
7
8
9
1
2
32
29
30
31
REF2
UVLO
BG
EN2
EN1
21
TEST
Technical Note
5/13
www.rohm.com
2011.05 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD95830MUV
Pin Descriptions
EN1 / EN2
When the input voltage on the EN pin reaches at least 2.2V, the switching regulator becomes active. At voltages less
than 0.3 V, the switching regulator becomes inactive, and the input current drops to 10µA or less. Thus the IC can be
controlled from 2.5V, 3.3V or 5V power supplies.
V
INS
The IC determines the duty cycles internally based upon the input voltage on this pin. Therefore, variations in voltage on
this pin can lead to highly unstable operation. This pin also acts as the voltage input to the internal switching regulator
block, and is sensitive to the impedance of the power supply. Attaching a bypass capacitor or RC filter on this pin as
appropriate for the application is recommended.
V
REG
Reference voltage output pin. If at least 2.2V is supplied to either the EN1 or EN2 pin, the reference output is switched on.
This pin supplies 5.0V at up to 10mA. Inserting a 2.2µF capacitor (with a X5R or X7R rating) between the VREG and
GND pins is recommended.
V
CC
This is the power supply pin for all internal circuitry. This pin can be supplied directly by a 5V source, or connect with the
V
REG
pin.
GND
This is the ground pin for all internal analog and digital power supplies.
V
OUT1 / VOUT2
This is the output voltage sense pin; this pin features an integrated discharge FET used to discharge the output capacitor
when status is set to OFF.
FB1 / FB2
This is the output feedback pin. FB is compared with REF (Refer to p.8) of IC. Set the output voltage with total about
10kΩ resistances.
V
IN1 / VIN2
This is the input voltage pin for Power supply. Connect a input capacitor as appropriate for the ripple current and the load
to the pin directly.
BOOT1 / BOOT2
This pin supplies voltage used for driving the high-side FET. Inserting a 0.1µF ceramic capacitor between the pin and SW
pins is recommended. Maximum absolute ratings are 21V from GND and 5.5V from SW. BOOT voltage swings between
(VIN + VREG) and VREG during active operation.
SW1 / SW2
This pin is connected to inductor (L). Maximum absolute rating is 15V from GND. SW voltage swings between V
IN and
PGND.
PGND1 / PGND2
This pin acts as the ground connection to the source of the low-side FET.
TEST
This is the pin for TEST. Connect to GND Pin
.
Technical Note
6/13
www.rohm.com
2011.05 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
BD95830MUV
Explanation of Operation
The BD95830MUV is a 2ch switching regulator controller incorporating ROHM’s proprietary H
3
Reg
TM
CONTROLLA control
system. When V
OUT drops due to a rapid load change, the system quickly restores VOUT by extending the ON time interval.
H
3
Reg
TM
control
(Normal operation)
(VOUT drops due to a rapid load change)
Timing Chart
Soft Start Function
FB
REF
HG
LG
HG(Gate of High side FET) output is determined by the
formula above.
LG(Gate of Low side FET) output operates until FB
voltage falls below REF voltage after HG becomes OFF.
When FB falls below the threshold voltage (REF), a drop is
detected, activating the H
3
Reg
TM
CONTROLLA system.
When FB (V
OUT) drops due to a rapid load change, and
the voltage remains below REF after the frequenc
y
becomes high, the system quickly restores VOUT by
extending the t
ON time, improving transient response.
Rush current
I
IN=
Co×V
OUT
1.3ms
[A]
Soft start is utilized when the EN pin is set high. Current
control takes effect at startup, enabling a moderate
“ramping start” on the output voltage. Soft start time is
1.3ms (typ). And rush current is determined via formula
(2) below.
(Co: All capacitors connected with V
OUT)
t
ON=
V
OUT
VIN
×
1
f
[sec]・・・(1)
・・・(2)
EN
REF
IIN
1.3ms
V
OUT
FB
REF
HG
I
OUT
LG

BD95830MUV-E2

Mfr. #:
Manufacturer:
Description:
Switching Voltage Regulators IC Pwr Swtch Reg Integrated FET
Lifecycle:
New from this manufacturer.
Delivery:
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