AD8344
Rev. 0 | Page 18 of 20
EVALUATION BOARD
An evaluation board is available for the AD8344. The evaluation
board is configured for single-ended signaling at the IF output
port via a balun transformer. The schematic for the evaluation
board is presented in Figure 48.
Table 5. Evaluation Boards Configuration Options
Component Function Default Conditions
R1, R2, R7,
C2, C4, C5, C6,
C12, C13, C14,
C15
Supply Decoupling.
Jumpers or power supply decoupling resistors and filter capacitors.
R1, R2, R7 = 0 Ω (Size 0603)
C4, C6, C13, C14 = 100 pF
(Size 0603)
C2, C5, C12, C15 = 0.1 µF
(Size 0603)
R3, R4 Jumpers in Single-Ended IF Output Circuit. 0 Ω (Size 0603)
R6, C11
R
BIAS
resistor that sets the bias current for the mixer core.
The capacitor provides ac bypass for R6.
R6 = 2.43 kΩ (Size 0603)
C11 = 100 pF (Size 0603)
R8 Jumper for pull down of the PWDN pin. R8 = 10 kΩ (Size 0603)
R9 Jumper. R9 = 0 Ω (Size 0603)
C3
RF Input AC Coupling. Provides dc block for RF input.
C3 = 100 pF (Size 0402)
C1
RF Common AC Coupling. Provides dc block for RF input common connection.
C1 = 100 pF (Size 0402)
C8
LO Input AC Coupling. Provides dc block for the LO input.
C8 = 100 pF (Size 0402)
C7
LO Common AC Coupling. Provides dc block for LO input common connection.
C7 = 100 pF (Size 0402)
SW1
Power Down. The part is on when the PWDN is connected to ground via SW1.
The part is disabled when PWDN is connected to the positive supply (V
S
) via SW1.
T1
IF Output Balun Transformer. Converts differential, high impedance IF output
to single-ended. When loaded with 50 Ω, this balun presents a 200 Ω load to the
mixers collectors. The center tap of the primary is used to supply the bias voltage
(V
S
) to the IF output pins.
T1 = TC4-1W, 4:1 (Mini-Circuits)
R11, Z3, Z4
R12, Z1, Z2
IF Output Interface—IFOP, IFOM. These positions can be used to modify the
impedance presented to the IF outputs.
R11 = 0 Ω (Size 0603)
Z3, Z4 = Open
R12 = 0 Ω (Size 0603)
Z1, Z2 = Open
AD8344
Rev. 0 | Page 19 of 20
04826-0-005
VPLO
LOCM
LOIN
COMM
VPDC
PWDN
EXRB
COMM
COMM
IFOP
IFOM
COMM
COMM
RFCM
RFIN
VPMX
AD8344
C1
100pF
C3
100pF
C6
100pF
C7
100pF
C8
100pF
C5
0.1µF
C4
100pF
C2
0.1µF
R2
0
R1
0
R7
0
R6
2.43k
C11
100pF
R10
0
R9
0
R3
0
R11
0
VPOS
VPOS
COMMON
POWER
DOWN
RF INPUT
LO
INPUT
Z1
OPEN
Z2
OPEN
R8
10k
Z3
OPEN
Z4
OPEN
R4
0
T1
TC4-1W
IF
OUTPUT
C14
100pF
C15
0.1µF
VPOS
SW1
C13
100pF
C12
0.1µF
Figure 48. Evaluation Board Schematic—Single-Ended IF Output
04826-0-007
Figure 49. Single-Ended Evaluation Board, Component Side Layout
04826-0-008
Figure 50. Single-Ended Evaluation Board, Component Side Silkscreen
AD8344
Rev. 0 | Page 20 of 20
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1 INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP VIEW
12° MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
1.65
1.50 SQ
*
1.35
BOTTOM
VIEW
16
5
13
8
9
12
4
*
COMPLIANTTO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body (CP-16-3)
Dimensions in millimeters
ORDERING GUIDE
Models Temperature Range Package Description Package Option Branding
AD8344ACPZ-REEL7
1
−40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP) CP-16-3 JHA
AD8344ACPZ-WP
1, 2
−40°C to +85°C 16-Lead Lead Frame Chip Scale Package (LFCSP) CP-16-3 JHA
AD8344-EVAL Evaluation Board
1
Z = Pb-free part.
2
WP = Waffle pack.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
D04826–0–6/04(0)

AD8344ACPZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Mixer IC 400MHz - 1.2GHz Active Receive
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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