1. General description
The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP
. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP
. Each
counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC4040: CMOS level
For 74HCT4040: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
74HC4040; 74HCT4040
12-stage binary ripple counter
Rev. 4 — 20 March 2014 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4040N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil);
long body
SOT38-1
74HCT4040N
74HC4040D 40 C to +125 C SO16 plastic small outline package; 16 leads; body
width 3.9 mm
SOT109-1
74HCT4040D
74HC4040DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
74HCT4040DB
