854S712 REVISION B 12/18/14 1 ©2014 Integrated Device Technology, Inc.
DATA SHEET
1:2 Fanout Buffer with Pre-Emphasis 854S712
General Description
The 854S712 is a differential, high-speed 1:2 data/clock fanout buffer
and line driver. The outputs support pre-emphasis in order to drive
backplanes and long transmission lines while reducing inter-symbol
interference effects. The pre-emphasis level is configurable to
optimize for low bit error rate or power consumption. Pre-emphasis
utilizes an increased output voltage swing for transition bits. The
device is optimized for data rates up to 4.5 Gbps (NRZ) and for
deterministic jitter in data applications and low additive jitter in clock
applications. The outputs are LVDS-compilant while the differential
input is compatible with a variety of signal levels such as LVDS,
LVPECL and CML. Internal input termination, a bias voltage output
for AC-coupling and small packaging (VFQFN) supports
space-efficient board designs. The 854S712 operates from a 3.3V
power supply and supports the industrial temperature range of -40°C
to +85°C.
Pin Assignment
Features
• 1:2 differential data/clock fanout buffer and line driver
• 4.5 Gbps data rate (NRZ) (maximum)
• Differential LVDS outputs
• Differential input supporting LVDS, LVPECL and CML levels
• Configurable output pre-emphasis
• Low-skew outputs: 10ps (maximum)
• Low data deterministic jitter: 4ps (maximum)
• LVCMOS interface levels for the control inputs
• Asynchronous output disable into high-impedance state
• Internal input termination: 100(Differential)
• Additive phase jitter, RMS: 0.08ps (typical)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
16-pin, 3mm x 3mm VFQFN Package
8XXXXXX
nIN
V
REF_AC
VTT
IN
2
3
4
1
854S712
12
11
10
9
16
15 14 13
GND
PE0
V
DD
PE1
nQ1
Q1
nQ0
Q0
V
DD
5
6
78
GND
nOE0
nOE1
nOE0
PE0
IN
nIN
V
TT
nOE1
PE1
V
REF_AC
Q0
nQ0
Q1
nQ1
VBB
50
50
