854S712 DATA SHEET
1:2 FANOUT BUFFER WITH PRE-EMPHASIS 10 REVISION B 12/18/14
Parameter Measurement Information, continued
1.2GHz NRZ (PRBS Pattern) GbE Mask, Pre-Emphasis On
Deterministic Jitter and Total Jitter (peak-to-peak)
Output Pre-Emphasis Voltage Ratio & Duration
2
Data Output
PATTERN
GENERATOR
Output
Pin
Input
Pin
AC COUPLED
EVALUATION
BOARD
HIGH-SPEED
SAMPLING
OSCILLOSCOPE
2 22
TP1 TP2
1010
Pre-Emphasis On HIGH
Pre-Emphasis Off HIGH
Pre-Emphasis Off LOW
Pre-Emphasis On LOW
nQx
Qx
Δtpe
Vpe
REVISION B 12/18/14 11 1:2 FANOUT BUFFER WITH PRE-EMPHASIS
854S712 DATA SHEET
Applications Information
3.3V Differential Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both V
SWING
and V
OH
must meet
the V
IN
and V
IH
input requirements. Figure 1A to Figure 1D show
interface examples for the IN/nIN input with built-in 50 terminations
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination
requirements.
Figure1A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure1B. IN/nIN Input with Built-In 50
Driven by a CML Driver with Open Collector
Figure1C. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure1D. IN/nIN Input with Built-In 50 Driven by a
CML Driver with Built-In 50 Pullup
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, we recommend that there
is no trace attached.
C1
C2
VT
V_REF_AC
50Ω
50Ω
3.3V CML with
Built-In Pullup
3.3V
IN
nIN
3.3V
Receiver with
Built-In 50Ω
Zo = 50Ω
Zo = 50Ω
854S712 DATA SHEET
1:2 FANOUT BUFFER WITH PRE-EMPHASIS 12 REVISION B 12/18/14
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z
T
) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z
0
) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 2A can be used
with either type of output structure. Figure 2B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
Figure2A. Standard LVDS Termination
Figure2B. Optional LVDS Termination
LVDS
Driver
Z
O
Z
T
Z
T
LVDS
Receiver
LVDS
Driver
Z
O
Z
T
LVDS
Receiver
C
Z
T
2
Z
T
2

854S712AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Diff. 1:2 Fanout Buffer and Line Drvr
Lifecycle:
New from this manufacturer.
Delivery:
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