REVISION B 12/18/14 7 1:2 FANOUT BUFFER WITH PRE-EMPHASIS
854S712 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "IFR2042 10kHz – 6.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
Additive Phase Jitter @ 491.52MHz
12kHz to 20MHz = 0.08ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
854S712 DATA SHEET
1:2 FANOUT BUFFER WITH PRE-EMPHASIS 8 REVISION B 12/18/14
Parameter Measurement Information
LVDS Output Load AC Test Circuit
Part-to-Part Skew
Output Pulse Skew
Differential Input Level
Output Skew
Output Enable/Disable Time
GND
tsk(pp)
Part 1
Part 2
t
PLH
t
PHL
tsk(p)
=
|t
PHL
-
t
PLH
|
V
IH
Cross Points
V
IN
V
IL
V
DD
/2 V
DD
/2
V
DD
/2
V
OL
V
OH
0V
V
DD
t
DIS
t
EN
Output Qx
nOEx
(Low-level
enabling)
REVISION B 12/18/14 9 1:2 FANOUT BUFFER WITH PRE-EMPHASIS
854S712 DATA SHEET
Parameter Measurement Information, continued
Propagation Delay
Single-Ended & Differential Input Voltage Swing
Offset Voltage Setup
Output Rise/Fall Time
Differential Output Voltage Setup
t
PD
V
IN
V
DIFF_IN
Differential Voltage Swing = 2 x Single-ended V
IN
20%
80%
80%
20%
t
R
t
F
V
OD

854S712AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Diff. 1:2 Fanout Buffer and Line Drvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet