CY29772
Document #: 38-07572 Rev. *A Page 10 of 12
Table 7. Suggested Oscillator Crystal Parameters
Parameter Description Conditions Min. Typ. Max. Unit
T
C
Frequency Tolerance ±1100 PPM
T
S
Frequency Temperature Stability (T
A
–10° to +60°C) ± 100 PPM
T
A
Aging (First three years @ 25°C) 5 PPM/Yr
C
L
Load Capacitance The crystal’s rated load 20 pF
R
ESR
Effective Series Resistance (ESR) 40 80 Ohm
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
Figure 2.
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
RT = 50 ohm
R
T = 50 ohm
Figure 3. LVCMOS_CLK AC Test Reference for V
DD
= 3.3V/2.5V
t(φ)
LVCMOS_CLK
FB_IN
VDD
GND
VDD/2
VDD
GND
VDD/2
Figure 4. LVCMOS Propagation Delay t(φ), Static Phase Offset
VDD
GND
VDD/2
tP
T0
DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (DC)
CY29772
Document #: 38-07572 Rev. *A Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Drawing and Dimension
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
t
SK(O)
VDD
GND
VDD/2
VDD
GND
VDD/2
Figure 6. Output-to-Output Skew, t
sk(O)
Ordering Information
Part Number Package Type Product Flow
CY29772AI 52-pin TQFP Industrial, –40°C to +85°C
CY29772AIT 52-pin TQFP – Tape and Reel Industrial,–40°C to 85°C
Lead-free
CY29772AXI 52-pin TQFP Industrial, –40°C to +85°C
CY29772AXIT 52-pin TQFP – Tape and Reel Industrial,–40°C to 85°C
52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
CY29772
Document #: 38-07572 Rev. *A Page 12 of 12
Document History Page
Document Title:CY29772 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Document Number: 38-07572
REV. ECN No. Issue Date
Orig. of
Change Description of Change
** 129007 09/03/03 RGL New Data Sheet
*A 395853 See ECN RGL
Added Lead-free devices
Added Jitter typical specs in the features section

CY29772AXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 2.5V or 3.3V 200MHz Delay Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet