CY29772
Document #: 38-07572 Rev. *A Page 8 of 12
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The CY29772 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. Figure 1 illus-
trates various waveforms for the SYNC output. Note that the
SYNC output is defined for all possible combinations of the QA
and QC outputs even though under some relationships the
lower frequency clock could be used as a synchronizing
signal.
Skew within Bank C – – 150
tsk(B) Bank-to-Bank Skew – – 325 ps
t
PLZ, HZ
Output Disable Time – – 8 ns
t
PZL, ZH
Output Enable Time – – 8 ns
BW PLL Closed-Loop Bandwidth
(–3 dB)
÷4 Feedback – 1.3–2.0 – MHz
÷6 Feedback – 0.7–1.3 –
÷8 Feedback – 0.9–1.3 –
÷10 Feedback – 0.6–1.1 –
÷12 Feedback – 0.6–0.9 –
÷16 Feedback – 0.–0.6 –
÷20 Feedback – 0.6–0.9 –
t
JIT(CC)
Cycle-to-Cycle Jitter Same frequency (125 MHz)
RMS (1σ)
–730ps
Same frequency – – 100
Multiple frequencies – – 375
t
JIT(PER)
Period Jitter Same frequency (125 MHz)
RMS (1σ)
–630ps
Same frequency – 45 75
Multiple frequencies – – 225
t
JIT(φ)
I/O Phase Jitter I/O same VDD – – 150 ps
t
LOCK
Maximum PLL Lock Time – – 1 ms
AC Parameters (V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C) (continued)
[6]
Parameter Description Condition Min. Typ. Max. Unit
