CY29772
Document #: 38-07572 Rev. *A Page 4 of 12
Table 6. Function Table (FB_OUT)
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT
0000÷8
0001÷12
0010÷16
0011÷20
0100÷16
0101÷24
0110÷32
0111÷40
1000÷4
1001÷6
1010÷8
1011÷10
1100÷8
1101÷12
1110÷16
1111÷20
CY29772
Document #: 38-07572 Rev. *A Page 5 of 12
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD
DC Supply Voltage –0.3 5.5 V
V
DD
DC Operating Voltage Functional 2.375 3.465 V
V
IN
DC Input Voltage Relative to V
SS
–0.3 V
DD
+ 0.3 V
V
OUT
DC Output Voltage Relative to V
SS
–0.3 V
DD
+ 0.3 V
V
TT
Output termination Voltage V
DD
÷ 2V
LU Latch-up Immunity Functional 200 mA
R
PS
Power Supply Ripple Ripple Frequency < 100 kHz 150 mVp-p
T
S
Temperature, Storage Non-functional –65 +150 °C
T
A
Temperature, Operating Ambient Functional –40 +85 °C
T
J
Temperature, Junction Functional +150 °C
Ø
JC
Dissipation, Junction to Case Functional 23 °C/W
Ø
JA
Dissipation, Junction to Ambient Functional 55 °C/W
ESD
H
ESD Protection (Human Body Model) 2000 V
FIT Failure in Time Manufacturing test 10 ppm
DC Electrical Specifications (V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
Parameter Description Condition Min. Typ. Max. Unit
V
IL
Input Voltage, Low LVCMOS 0.7 V
V
IH
Input Voltage, High LVCMOS 1.7 V
DD
+0.3 V
V
OL
Output Voltage, Low
[4]
I
OL
= 15 mA 0.6 V
V
OH
Output Voltage, High
[4]
I
OH
= –15 mA 1.8 V
I
IL
Input Current, Low
[5]
V
IL
= V
SS
–100 µA
I
IH
Input Current, High
[5]
V
IL
= V
DD
––100µA
I
DDA
PLL Supply Current AVDD only 5 10 mA
I
DDQ
Quiescent Supply Current All VDD pins except AVDD 8 mA
I
DD
Dynamic Supply Current Outputs loaded @ 100 MHz 135 mA
C
IN
Input Pin Capacitance 4 pF
Z
OUT
Output Impedance 14 18 22
DC Electrical Specifications (V
DD
= 3.3V ± 5%, T
A
= –40°C to +85°C)
Parameter Description Condition Min. Typ. Max. Unit
V
IL
Input Voltage, Low LVCMOS 0.8 V
V
IH
Input Voltage, High LVCMOS 2.0 V
DD
+ 0.3 V
V
OL
Output Voltage, Low
[4]
I
OL
= 24 mA 0.55 V
I
OL
= 12 mA 0.30
V
OH
Output Voltage, High
[4]
I
OH
= –24 mA 2.4 V
I
IL
Input Current, Low
[5]
V
IL
= V
SS
–100 µA
I
IH
Input Current, High
[5]
V
IL
= V
DD
––100µA
I
DDA
PLL Supply Current AVDD only 5 10 mA
I
DDQ
Quiescent Supply Current All VDD pins except AVDD 8 mA
I
DD
Dynamic Supply Current Outputs loaded @ 100 MHz 225 mA
C
IN
Input Pin Capacitance 4 pF
Z
OUT
Output Impedance 12 15 18
Notes:
4. Driving one 50 parallel-terminated transmission line to a termination voltage of V
TT
. Alternatively, each output drives up to two 50 series-terminated transmis-
sion lines.
5. Inputs have pull-up or pull-down resistors that affect the input current.
CY29772
Document #: 38-07572 Rev. *A Page 6 of 12
AC Electrical Specifications (V
DD
= 2.5V ± 5%, T
A
= –40°C to +85°C)
[6]
Parameter Description Condition Min. Typ. Max. Unit
f
VCO
VCO Frequency 200
380 MHz
f
XTAL
Crystal Frequency Range See Table 7 10
25 MHz
f
in
Input Frequency ÷4 Feedback 50
95 MHz
÷6 Feedback 33.3
63.3
÷8 Feedback 25
47.5
÷10 Feedback 20
38
÷12 Feedback 16.6
31.6
÷16 Feedback 12.5
23.75
÷20 Feedback 10
19
÷24 Feedback 8.3
15.8
÷32 Feedback 6.25
11.8
÷40 Feedback 5
9.5
Bypass mode (PLL_EN = 0) 0
200
f
refDC
Input Duty Cycle 25
75 %
t
r
, t
f
TCLK Input Rise/FallTime 0.7V to 1.7V
1.0 ns
f
MAX
Maximum Output Frequency ÷2 Output 100
190 MHz
÷4 Output 50
95
÷6 Output 33.3
63.3
÷8 Output 25
47.5
÷10 Output 20 38
÷12 Output 16.6 31.6
÷16 Output 12.5 23.75
÷20 Output 10 19
÷24 Output 8.3 15.8
f
SCLK
Serial Clock Frequency 20 MHz
DC Output Duty Cycle f
MAX
< 100 MHz 47.5 52.5 %
f
MAX
> 100 MHz 45 55
t
r
, t
f
Output Rise/Fall times 0.6V to 1.8V 0.1 1.0 ns
t
(φ)
Propagation Delay
(static phase offset)
TCLK to FB_IN –125 125 ps
t
sk(O)
Output-to-Output Skew Skew within Bank A 75 ps
Skew within Bank B 100
Skew within Bank C 150
t
sk(B)
Bank-to-Bank Skew 400 ps
t
PLZ, HZ
Output Disable Time 10 ns
t
PZL, ZH
Output Enable Time 10 ns
BW PLL Closed Loop Bandwidth
(–3 dB)
÷4 Feedback 1.3–2.0 MHz
÷6 Feedback 0.7–1.3
÷8 Feedback 0.9–1.3
÷10 Feedback 0.6–1.1
÷12 Feedback 0.6–0.9
÷16 Feedback 0.4–0.6
÷20 Feedback 0.6–0.9
Note:
6. AC characteristics apply for parallel output termination of 50 to V
TT
. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.

CY29772AXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 2.5V or 3.3V 200MHz Delay Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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