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CY7C135-25JXI

P1-P3P4-P6P7-P9P10-P12
CY7C135, CY7C135A
CY7C1342
4K x 8 Dual-Port Static RAM and 4K x 8
Dual-Port SRAM with Semaphores
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-06038 Rev. *D Revised December 09, 2008
Features
■
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■
4K x 8 organization
■
0.65 micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: I
CC
= 160 mA (max)
■
Fully asynchronous operation
■
Automatic power down
■
Semaphores included on the 7C1342 to permit software
handshaking between ports
■
Available in 52-pin PLCC
■
Pb-free packages available
Functional Description
The CY7C135/135A
[1]
and CY7C1342 are high speed CMOS 4K
x 8 dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
location in memory. Application areas include interpro-
cessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE
), read
or write enable (R/W
), and output enable (OE). The
CY7C135/135A is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore, the
user must be aware that simultaneous access to a location is
possible. Semaphores are offered on the CY7C1342 to assist in
arbitrating between ports. The semaphore logic is comprised of
eight shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates that
a shared resource is in use. An automatic power down feature is
controlled independently on each port by a chip enable (CE
) pin
or SEM
pin (CY7C1342 only).
The CY7C135/135A and CY7C1342 are available in 52-pin
PLCC.
R/W
L
CE
L
OE
L
A
11L
A
0L
A
0R
A
11R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
SEMAPHORE
ARBITRATION
(7C1342 only)
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
(7C1342 only)
SEM
L
SEM
R
(7C1342 only)
Logic Block Diagram
Note
1. CY7C135 and CY7C135A are functionally identical
[+] Feedback
CY7C135, CY7C135A
CY7C1342
Document #: 38-06038 Rev. *D Page 2 of 12
Pin Configurations
Figure 1. Pin Diagram - CY7C135/135A (Top View) Figure 2. Pin Diagram - CY7C1342 (Top View)
Selection Guide
Parameter
7C135-15
7C1342-15
7C135-20
7C1342-20
7C135/135A-25
7C1342-25
7C135-35
7C1342-35
7C135-55
7C1342-55
Unit
Maximum Access Time 15 20 25 35 55 ns
Maximum Operating Current Commercial 220 190 180 160 160 mA
Maximum Standby Current for
I
SB1
Commercial 60 50 40 30 30 mA
1
V
CC
7C135/135A
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L
5L
6L
7L
0R
1R
2R
3R
4R
5R
6R
NC
GND
OE
N/C
A
R/W
CE
R/W
0L
L
L
L
CE
R
R
A
10L
A
10R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
N/C
A
11R
A
11L
A
11R
1
V
CC
7C1342
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L
5L
6L
7L
0R
1R
2R
3R
4R
5R
6R
NC
GND
OE
SEM
A
R/W
CE
R/W
SEM
0L
L
L
L
L
CE
R
R
R
A
10L
A
10R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
A
11L
Pin Definitions
Left Port Right Port Description
A
0L–11L
A
0R–11R
Address Lines
CE
L
CE
R
Chip Enable
OE
L
OE
R
Output Enable
R/W
L
R/W
R
Read/Write Enable
SEM
L
(CY7C1342
only)
SEM
R
(CY7C1342
only)
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least
significant bits of the address lines determines which semaphore to write or read. The I/O
0
pin
is used when writing to a semaphore. Semaphores are requested by writing a 0 into the
respective location.
[+] Feedback
CY7C135, CY7C135A
CY7C1342
Document #: 38-06038 Rev. *D Page 3 of 12
Maximum Ratings
[2]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ..................................–65°C to+150°C
Ambient Temperature with
Power Applied .............................................–55°C to+125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)............................................ –0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State................................................ –0.5V to+7.0V
DC Input Voltage
[3]
.........................................–3.0V to +7.0V
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current ....................................................> 200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial 0
°
C to +70
°
C 5V ± 10%
Industrial –40
°
C to +85
°
C 5V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
7C135-15
7C1342-15
7C135-20
7C1342-20
7C135-25
7C135A-25
7C1342-25
Unit
Min Max Min Max Min Max
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA 2.4 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 4.0 mA 0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 2.2 2.2 V
V
IL
Input LOW Voltage 0.8 0.8 0.8 V
I
IX
Input Load Current GND ≤ V
I
≤ V
CC
–10 +10 –10 +10 –10 +10 μA
I
OZ
Output Leakage Current Outputs Disabled,
GND ≤ V
O
≤ V
CC
–10 +10 –10 +10 –10 +10 μA
I
CC
Operating Current V
CC
= Max.,
I
OUT
= 0 mA
Com’l 220 190 180 mA
Ind. 190
I
SB1
Standby Current
(Both Ports TTL Levels)
CE
L
and CE
R
≥ V
IH
,
f = f
MAX
[4]
Com’l 60 50 40 mA
Ind. 50
I
SB2
Standby Current
(One Port TTL Level)
CE
L
and CE
R
≥ V
IH
,
f = f
MAX
[4]
Com’l 130 120 110 mA
Ind. 120
I
SB3
Standby Current
(Both Ports CMOS Levels)
Both Ports CE and CE
R
≥ V
CC
–
0.2V,
V
IN
≥ V
CC
– 0.2V
or V
IN
≤ 0.2V, f = 0
[4]
Com’l 15 15 15 mA
Ind. 30
I
SB4
Standby Current
(One Port CMOS Level)
One Port CE
L
or
CE
R
≥ V
CC
– 0.2V,
V
IN
≥V
CC
– 0.2V or
V
IN
≤ 0.2V,
Active Port Outputs,
f = f
MAX
[4]
Com’l 125 115 100 mA
Ind. 115
Notes
2. The voltage on any input or I/O pin cannot exceed the power pin during power up.
3. Pulse width < 20 ns.
4. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
I
SB3.
[+] Feedback
P1-P3P4-P6P7-P9P10-P12

CY7C135-25JXI

Mfr. #:
Buy CY7C135-25JXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Kx8 32Kb 25ns DUAL PORT SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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