CY7C135, CY7C135A
CY7C1342
Document #: 38-06038 Rev. *D Page 9 of 12
Architecture
The CY7C135/135A consists of an array of 4K words of 8 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE
, OE, R/W). Two semaphore control pins exist for the
CY7C1342 (SEM
L/R
).
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W
to guarantee a valid write. Because there is no on-chip
arbitration, the user must be sure that a specific location is not
accessed simultaneously by both ports or erroneous data could
result. A write operation is controlled by either the OE
pin (see
Figure 7) or the R/W
pin (see Figure 8). Data can be written
t
HZOE
after the OE is deasserted or t
HZWE
after the falling edge
of R/W
. Required inputs for write operations are summarized in
Table 1.
If a location is being written to by one port and the opposite port
attempts to read the same location, a port-to-port flowthrough
delay is met before the data is valid on the output. Data is valid
on the port wishing to read the location t
DDD
after the data is
presented on the writing port.
Read Operation
When reading the device, the user must assert both the OE and
CE
pins. Data is available t
ACE
after CE or t
DOE
after OE are
asserted. If the user of the CY7C1342 wishes to access a
semaphore, the SEM
pin must be asserted instead of the CE pin.
Required inputs for read operations are summarized in Table 1.
Semaphore Operation
The CY7C1342 provides eight semaphore latches, which are
separate from the dual port memory locations. Semaphores are
used to reserve resources which are shared between the two
ports. The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM
or OE must be
deasserted for t
SOP
before attempting to read the semaphore.
The semaphore value is available t
SWRD
+ t
DOE
after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control over the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has relin-
quished control of the semaphore (by writing a one), the left side
succeeds in gaining control of the semaphore. If the left side no
longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM
LOW. The SEM
pin functions as a chip enable for the semaphore latches. CE
must remain HIGH during SEM LOW. A
0–2
represents the
semaphore address. OE
and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
0
is used. If a 0 is written
to the left port of an unused semaphore, a one appears at the
same semaphore address on the right port. That semaphore can
now only be modified by the side showing a zero (the left port in
this case). If the left port now relinquishes control by writing a one
to the semaphore, the semaphore is set to one for both sides.
However, if the right port had requested the semaphore (written
a zero) while the left port had control, the right port would immedi-
ately own the semaphore. Table 2 shows sample semaphore
operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports request a semaphore control by
writing a 0 to a semaphore within t
SPS
of each other, it is
guaranteed that only one side gains access to the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program during power up. All semaphores on
both sides should have a one written into them at initialization
from both sides to assure that they are free when needed.
Table 1. Non-Contending Read/Write
Inputs Outputs
Operation
CE R/W OE SEM I/O
0
– I/O
7
H X X H High Z Power Down
H H L L Data Out Read Semaphore
X X H X High Z I/O Lines Disabled
H L X L Data In Write to Semaphore
LHL HData OutRead
LLXHData In Write
L X X L Illegal Condition
Table 2. Semaphore Operation Example
Function
I/O
0-7
Left
I/O
0-7
Right
Status
No action 1 1 Semaphore free
Left port writes
semaphore
0 1 Left port obtains
semaphore
Right port writes 0 to
semaphore
0 1 Right side is denied
access
Left port writes 1 to
semaphore
1 0 Right port is granted
access to Semaphore
Left port writes 0 to
semaphore
1 0 No change. Left port is
denied access
Right port writes 1 to
semaphore
0 1 Left port obtains
semaphore
Left port writes 1 to
semaphore
1 1 No port accessing
semaphore address
Right port writes 0 to
semaphore
1 0 Right port obtains
semaphore
Right port writes 1 to
semaphore
1 1 No port accessing
semaphore
Left port writes 0 to
semaphore
0 1 Left port obtains
semaphore
Left port writes 1 to
semaphore
1 1 No port accessing
semaphore
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