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CY7C135-25JXI

P1-P3P4-P6P7-P9P10-P12
CY7C135, CY7C135A
CY7C1342
Document #: 38-06038 Rev. *D Page 4 of 12
Electrical Characteristics
Over the Operating Range
(continued)
Parameter Description Test Conditions
7C135-35
7C1342-35
7C135-55
7C1342-55
Unit
Min Max Min Max
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 4.0 mA 0.4 0.4 V
V
IH
2.2 2.2 V
V
IL
Input LOW Voltage 0.8 0.8 V
I
IX
Input Load Current GND ≤ V
I
≤ V
CC
–10 +10 –10 +10 μA
I
OZ
Output Leakage Current Outputs Disabled, GND ≤ V
O
≤ V
CC
–10 +10 –10 +10 μA
I
CC
Operating Current V
CC
= Max., I
OUT
= 0 mA Com’l 160 160 mA
V
CC
= Max., I
OUT
= 0 mA Ind. 180 180
I
SB1
Standby Current
(Both Ports TTL Levels)
CE
L
and CE
R
≥ V
IH
, f = f
MAX
[4]
Com’l 30 30 mA
Ind. 40 40
I
SB2
Standby Current
(One Port TTL Level)
CE
L
and CE
R
≥ V
IH
, f = f
MAX
[4]
Com’l 100 100 mA
Ind. 110 110
I
SB3
Standby Current
(Both Ports CMOS Levels)
Both Ports CE and CE
R
≥ V
CC
– 0.2V,
V
IN
≥ V
CC
– 0.2V
or V
IN
≤ 0.2V, f = 0
[4]
Com’l 15 15 mA
Ind. 30 30
I
SB4
Standby Current
(One Port CMOS Level)
One Port CE
L
or CE
R
≥ V
CC
– 0.2V,
V
IN
≥ V
CC
– 0.2V or V
IN
≤ 0.2V,
Active Port Outputs, f = f
MAX
[4]
Com’l 90 90 mA
Ind. 100 100
Capacitance
[5]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
10 pF
C
OUT
Output Capacitance 10 pF
Figure 3. AC Test Loads and Waveforms
Note
5. Tested initially and after any design or process changes that may affect these parameters.
3.0V
GND
90%
90%
10%
≤ 3ns
≤3
ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 893Ω
5V
OUTPUT
R1 = 347Ω
C = 30 pF
R
TH
= 250Ω
V
TH
=
1.4V
OUTPUT
C = 30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
V
X
OUTPUT
R
TH
= 250Ω
C = 5 pF
[+] Feedback
CY7C135, CY7C135A
CY7C1342
Document #: 38-06038 Rev. *D Page 5 of 12
Switching Characteristics
Over the Operating Range
[6]
Parameter Description
7C135-15
7C1342-15
7C135-20
7C1342-20
7C135-25
7C135A-25
7C1342-25
7C135-35
7C1342-35
7C135-55
7C1342-55
Unit
Min Max Min Max Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 15 20 25 35 55 ns
t
AA
Address to Data Valid 15 20 25 35 55 ns
t
OHA
Output Hold From Address Change 3 3 3 3 3 ns
t
ACE
CE LOW to Data Valid 15 20 25 35 55 ns
t
DOE
OE LOW to Data Valid 10 13 15 20 25 ns
t
LZOE
[7,8,9]
OE Low to Low Z 33333ns
t
HZOE
[7,8,9]
OE HIGH to High Z 10 13 15 20 25 ns
t
LZCE
[7,8,9]
CE LOW to Low Z 33333ns
t
HZCE
[7,8,9]
CE HIGH to High Z 10 13 15 20 25 ns
t
PU
[9]
CE LOW to Power Up 00000ns
t
PD
[9]
CE HIGH to Power Down 15 20 25 35 55 ns
Write Cycle
t
WC
Write Cycle Time 15 20 25 35 55 ns
t
SCE
CE LOW to Write End 12 15 20 30 50 ns
t
AW
Address Setup to Write End 12 15 20 30 50 ns
t
HA
Address Hold from Write End 2 2 2 2 2 ns
t
SA
Address Setup to Write Start 0 0 0 0 0 ns
t
PWE
Write Pulse Width 12 15 20 25 50 ns
t
SD
Data Setup to Write End 10 13 15 15 25 ns
t
HD
Data Hold from Write End 0 0 0 0 0 ns
t
HZWE
[8,9]
R/W LOW to High Z 10 13 15 20 25 ns
t
LZWE
[8,9]
R/W HIGH to Low Z 3 3 3 3 3 ns
t
WDD
[10]
Write Pulse to Data Delay 30 40 50 60 70 ns
t
DDD
[10]
Write Data Valid to Read Data Valid 25 30 30 35 40 ns
Semaphore Timing
[11]
t
SOP
SEM Flag Update Pulse
(OE
or SEM)
10 10 10 15 15 ns
t
SWRD
SEM Flag Write to Read Time 5 5 5 5 5 ns
t
SPS
SEM Flag Contention Window 5 5 5 5 5 ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30 pF load capacitance.
7. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
8. Test conditions used are Load 3.
9. This parameter is guaranteed but not tested.
10. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 6.
11. Semaphore timing applies only to CY7C1342.
[+] Feedback
CY7C135, CY7C135A
CY7C1342
Document #: 38-06038 Rev. *D Page 6 of 12
Switching Waveforms
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
Either Port Address Access
Figure 4. Read Cycle No. 1
[12,13]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
SEM
or CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
Either Port CE/OEAccess
Figure 5. Read Cycle No. 2
[12,14]
[11]
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA
INR
DATA
OUTL
t
wc
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
Figure 6. Read Timing with Port-to-Port
[15]
Notes
12. R/W
is HIGH for read cycle.
13. Device is continuously selected, CE
= V
IL
and OE =
V
IL
.
14. Address valid prior to or coincident with CE
transition LOW.
15. CE
L
= CE
R
=LOW; R/W
L
= HIGH
[+] Feedback
P1-P3P4-P6P7-P9P10-P12

CY7C135-25JXI

Mfr. #:
Buy CY7C135-25JXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Kx8 32Kb 25ns DUAL PORT SRAM
Lifecycle:
New from this manufacturer.
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