NCP3012
http://onsemi.com
10
DETAILED DESCRIPTION
OVERVIEW
The NCP3012 operates as a 75 kHz, voltage−mode,
pulse−width−modulated, (PWM) synchronous buck
converter. It drives high−side and low−side N−channel
power MOSFETs. The NCP3012 incorporates an internal
boost circuit consisting of a boost Clamp and boost diode to
provide supply voltage for the high side MOSFET Gate
driver. The NCP3012 also integrates several protection
features including input undervoltage lockout (UVLO),
output undervoltage (OUV), output overvoltage (OOV),
adjustable high−side current limit (I
SET
and I
LIM
), and
thermal shutdown (TSD). The NCP3012 includes a
Power Good (PG) open drain output which flags out of
regulation conditions.
The operational transconductance amplifier (OTA)
provides a high gain error signal which is compared to the
internal ramp signal using the PWM comparator. This
results in a voltage mode PWM feedback stage. The PWM
signal is sent to the internal gate drivers to modulate
MOSFET on and off times. The gate driver stage
incorporates symmetrical fixed non−overlap time between
the high−side and low−side MOSFET gate drives.
The NCP3012 has a dual function Master/Slave SYNC
pin In Slave mode, the NCP3012 synchronizes to an external
clock signal. In Master mode, the NCP3012 can output a
phase shifted clock signal to drive another master slave
equipped power stage to provide a 180° switching
relationship between the power stages. This can help to
reduce the required input filter capacitance in multi−stage
power converters.
The external 1.25 V reference voltage (VREF) is
provided for system level use. It remains active even when
the NCP3012 is disabled.
POR and UVLO
The device contains an internal Power On Reset (POR)
and input Undervoltage Lockout (UVLO) that inhibits the
internal logic and the output stage from operating until V
CC
reaches their respective predefined voltage levels. The
internal logic takes approximately 50 ms to check the SYNC
pin and determine if the device is in Master mode or Slave
mode once the voltage at V
CC
exceeds the rising UVLO
threshold. The device remains in Standby if enable is not
asserted following the 50 ms time period.
Enable/Disable
The device has an enable pin (EN) with internal 50 mA
pullup current. This gives the user the option of driving EN
with a push−pull or open−drain/collector enable signal.
When driving EN with an external logic supply a 10 kW
series current limiting resistor must be placed in series with
EN. See Figure 18. The maximum enable threshold is 3.4 V.
If no external drive voltage is available, the internal pullup
can be used to enable the device, and an open drain/collector
input, such as a MOSFET or BJT can be used to disable the
device. A capacitor connected between EN and ground can
be used with the internal pullup current source to provide a
fixed delay to turn−on and turn off. See Equation 1.
DISABLE ENABLE
EN
V
EN
−or−
− or−
DISABLEENABLE
DISABLEENABLE
10 k
W
Enable
Logic
Figure 18. Enable Circuits: Push−Pull, Open−Drain,
or Open−Collector
C
EN_DLY
+
I
PU
T
EN_DLY
V
EN_TH
(eq. 1)
C
EN_DLY
= Delay Capacitance (F)
I
PU
= Pullup Current
V
EN_TH
= Enable Input High Threshold Voltage
T
EN_DLY
= Desired Delay Time
