[AK4127]
MS0593-E-02 2010/05
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Input PORT (Master mode)
IBICK Frequency
IBICK Duty
IBICK “” to ILRCK
SDTI Hold Time from IBICK “
SDTI Setup Time to IBICK “
fBCK
dBCK
tMBLR
tSDH
tSDS
20
15
15
64fs
50
20
Hz
%
ns
ns
ns
Output PORT (Slave mode)
OBICK Period (8kHz 54kHz)
(54kHz 108kHz)
(108kHz 216kHz)
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “” (
Note 8)
OBICK “” to OLRCK Edge (
Note 8)
OLRCK to SDTO (MSB) (Except I
2
S mode)
OBICK “” to SDTO
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/256fs
1/128fs
1/64fs
27
27
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output PORT (TDM slave mode)
OBICK Period
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to BICK “ (
Note 8)
OBICK “” to LRCK Edge (
Note 8)
OBICK “” to SDTO
TDMIN Hold Time
TDMIN Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
20
10
20
ns
ns
ns
ns
ns
ns
ns
ns
Output PORT (Master mode)
OBICK Frequency
OBICK Duty
OBICK “” to OLRCK
OBICK “” to SDTO
fBCK
dBCK
tMBLR
tBSD
20
20
64fs
50
20
20
Hz
%
ns
ns
Reset Timing
PDN Pulse Width (
Note 9)
tPD
150
ns
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4127 can be reset by bringing the PDN pin = “L”.
[AK4127]
MS0593-E-02 2010/05
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Timing Diagram
1/fCLK
MCLK
tCLKH tCLKL
VIH
VIL
1/fs
LRCK
VIH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
Clock Timing
LRCK
VIH
VIL
tBLR
BICK
VIH
VIL
tLRS
SDTO 50%DVDD
tLRB
tBSD
tSDS
SDTI
VIL
tSDH
VIH
Audio Interface Timing (Slave mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
[AK4127]
MS0593-E-02 2010/05
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LRCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI
VIL
tSDH
VIH
tMBLR
dBCK
50%DVDD
Audio Interface Timing (Master mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
tPD
PDN
VIL
Power Down & Reset Timing

AK4127VF

Mfr. #:
Manufacturer:
Description:
IC SRC 2 CHAN 192KHZ 30VSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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