[AK4127]
MS0593-E-02 2010/05
- 5 -
PIN/FUNCTION
No. Pin Name I/O Function
1 FILT O PLL Loop Filter Pin, Hi-Z when PDN pin = “L”.
2 AVSS - Analog Ground Pin
3 PDN I
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
4 SMUTE I
Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
5 DITHER I
Dither Enable Pin
“H” : Dither ON, “L” : Dither OFF
6 PLL2 I PLL Mode Select 2 Pin
7 ILRCK I/O Input Channel Clock Pin, Output “L” when PDN = “L” and master mode.
8 IBICK I/O Audio Serial Data Clock Pin, Output “L” when PDN = “L” and master mode.
9 SDTI I Audio Serial Data Input Pin
10 IDIF0 I Audio Interface Format 0 Pin for Input PORT
11 IDIF1 I Audio Interface Format 1 Pin for Input PORT
12 IDIF2 I Audio Interface Format 2 Pin for Input PORT
13 PLL0 I PLL Mode Select 0 Pin
14 PLL1 I PLL Mode Select 1 Pin
15 UNLOCK O Unlock Status Pin, Output “H” when PDN = “L”
16 OBIT0 I Bit Length Select 0 Pin for Output Data
17 OBIT1 I Bit Length Select 1 Pin for Output Data
18 IMCLK I Master Clock Input Pin for Input PORT
19 CMODE0 I Clock Mode Select 0 Pin
20 CMODE1 I Clock Mode Select 1 Pin
21 CMODE2 I Clock Mode Select 2 Pin
22 ODIF0 I Audio Interface Format 0 Pin for Output PORT
23 ODIF1 I Audio Interface Format 1 Pin for Output PORT
24 SDTO O Audio Serial Data Output Pin for Output PORT, Output “L” when PDN pin = “L”
25 OBICK I/O
Audio Serial Data Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
26 OLRCK I/O
Output Channel Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
27 OMCLK I
Master Clock/TDM Data Input Pin for Output PORT
OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”)
TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”)
28 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
29 DVSS - Digital Ground Pin
30 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V
Note: All input pins must not be left floating.
