[AK4127]
MS0593-E-02 2010/05
- 13 -
OPERATION OVERVIEW
■ System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0 ∼ 3 of
Table 2) or IBICK (Mode 4 ∼ 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And
an internal system clock is created by IMCLK (Mode 8 ∼ 15 of
Table 2) in master mode. The PLL2-0 pins and IDIF2-0
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =
“L”. When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the
TDM mode at the output port.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode IDIF2 IDIF1 IDIF0 SDTI Format ILRCK IBICK IBICK Freq Master / Slave
0 L L L 16bit, LSB justified
≥ 32fsi
1 L L H 20bit, LSB justified
≥ 40fsi
2 L H L 24/20bit, MSB justified
≥ 48fsi
3 L H H 24/16bit, I
2
S Compatible
≥ 48fsi or 32fsi
4 H L L 24bit, LSB justified
Input Input
≥ 48fsi
Slave
5 H L H 24bit, MSB justified 64fs
6 H H L 24bit, I
2
S Compatible
Output Output
64fs
Master
7 H H H Reserved
Table 1. Input Audio Interface Format (Input PORT)
Mode
Master / Slave PLL2 PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK
SMUTE
(
Note 14)
0 L L L
8k ∼ 96kHz
1 L L H
Manual
2 L H L
Semi-Auto
3 L H H
8k ∼ 216kHz
16k ∼ 216kHz
(
Note 10)
Depending
on IDIF2-0
(
Note 11)
Not
needed.
(
Note 13)
Manual
4 H L L
32fsi
(
Note 12)
5 H L H 64fsi
6 H H L 128fsi
Manual
7
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
H H H
8k ∼ 216kHz
(
Note 11)
64fsi
Not
needed.
(
Note 13)
Semi-Auto
8 L L L
8k ∼ 216kHz
128fsi
9 L L H
8k ∼ 108kHz
256fsi
10 L H L
8k ∼ 54kHz
512fsi
Manual
11 L H H
8k ∼ 216kHz
128fsi
Semi-Auto
12 H L L
8k ∼ 216kHz
192fsi
13 H L H
8k ∼ 108kHz
384fsi
14 H H L
8k ∼ 54kHz
768fsi
Manual
15
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
H H H
8k ∼ 216kHz
64fsi
192fsi
Semi-Auto
Table 2. PLL Setting (Input PORT)
Note 10. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 11. The IBCIK must be continuous except when the clocks are changed.
Note 12. IBCIK = 32fsi is supported only 16bit LSB justified and I
2
S Compatible.
Note 13. Fixed to DVSS.
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
