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KSZ8721CL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
KS8721CL Micrel, Inc.
M9999-041405 4 April 2005
Table Of Contents
Pin Description ............................................................................................................................................................ 6
Strapping Option ......................................................................................................................................................... 9
Pin Configuration ...................................................................................................................................................... 10
Introduction ........................................................................................................................................................... 11
100BASE-TX Transmit ........................................................................................................................................ 11
100BASE-TX Receive ......................................................................................................................................... 11
PLL Clock Synthesizer......................................................................................................................................... 11
Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 11
10BASE-T Transmit ............................................................................................................................................. 11
10BASE-T Receive .............................................................................................................................................. 11
SQE and Jabber Function (10BASE-T only) ....................................................................................................... 11
Auto-Negotiation .................................................................................................................................................. 11
MII Management Interface................................................................................................................................... 12
MII Data Interface ................................................................................................................................................ 12
Transmit Clock ............................................................................................................................................. 12
Receive Clock .............................................................................................................................................. 12
Transmit Enable ........................................................................................................................................... 12
Receive Data Valid ...................................................................................................................................... 12
Error Signals ................................................................................................................................................ 12
Carrier Sense ............................................................................................................................................... 12
Collision ........................................................................................................................................................ 13
RMII (Reduced MII) Data Interface ..................................................................................................................... 13
RMII Signal Definition .......................................................................................................................................... 13
Reference Clock .................................................................................................................................................. 13
Carrier Sense/Receive Data Valid ....................................................................................................................... 13
Receive Data ....................................................................................................................................................... 13
Transmit Enable................................................................................................................................................... 13
Transmit Data ...................................................................................................................................................... 14
Collision Detection ............................................................................................................................................... 14
RX_ER ........................................................................................................................................................... 14
RMII AC Characteristics ...................................................................................................................................... 14
Unused RMII Pins ................................................................................................................................................ 14
Auto-Crossover (Auto-MDI/MDI-X) ...................................................................................................................... 15
Power Management ............................................................................................................................................. 16
100BT FX Mode .................................................................................................................................................. 16
Media Converter Operation ................................................................................................................................. 16
Circuit Design Reference for Power Supply ........................................................................................................ 17
Register Map ........................................................................................................................................................... 18
Register 0h: Basic Control .................................................................................................................................. 18
Register 1h: Basic Status ................................................................................................................................... 18
Register 2h: PHY Identifier 1 .............................................................................................................................. 19
Register 3h: PHY Identifier 2 .............................................................................................................................. 19
Register 4h: Auto-Negotiation Advertisement ..................................................................................................... 19
Register 5h: Auto-Negotiation Link Partner Ability .............................................................................................. 19
Register 6h: Auto-Negotiation Expansion ........................................................................................................... 20
Register 7h: Auto-Negotiation Next Page ........................................................................................................... 20
Register 8h: Link Partner Next Page Ability ........................................................................................................ 20
April 2005 5 M9999-041405
KS8721CL Micrel, Inc.
Register Map (continued)
Register 15h: RXER Counter...................................................................................................................................... 21
Register 1bh: Interrupt Control/Status Register.......................................................................................................... 21
Register 1fh: 100BASE-TX PHY Controller ................................................................................................................ 21
Absolute Maximum Ratings........................................................................................................................................ 23
Operating Ratings ........................................................................................................................................................ 23
Electrical Characteristics ............................................................................................................................................ 23
Timing Diagrams .......................................................................................................................................................... 25
Selection of Isolation Transformer ............................................................................................................................ 31
Selection of Reference Crystal ................................................................................................................................... 31
Package Information ................................................................................................................................................... 32
KS8721CL Micrel, Inc.
M9999-041405 6 April 2005
Pin Description
Pin Number Pin Name Type
(1)
Pin Function
1 MDIO I/O Management Independent Interface (MII) Data I/O. This pin requires an external
4.7K pull-up resistor.
2 MDC I MII Clock Input. This pin is synchronous to the MDIO.
3 RXD3/ Ipd/O MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
PHYAD When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See
“Strapping Options” section for details.
4 RXD2/ Ipd/O MII Receive Data Output.
PHYAD2 During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See
“Strapping Options” section for details.
5 RXD1/ Ipd/O MII Receive Data Output.
PHYAD3 During reset, the pull-up/pull-down value is latched as PHYADDR [3]. See
“Strapping Options” section for details.
6 RXD0/ Ipd/O MII Receive Data Output.
PHYAD4 During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See
“Strapping Options” section for details.
7 VDDIO P Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage
regulator. See “Circuit Design Ref. for Power Supply" section for details.
8 GND GND Ground.
9RXDV/ Ipd/O MII Receive Data Valid Output.
CRSDV/ During reset, the pull-up/pull-down value is latched as PCS_LPBK. See
PCS_LPBK “Strapping Options” section for details.
10 RXC O MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
11 RXER/ISO Ipd/O MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
12 GND GND Ground.
13 VDDC P Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply"
section for details.
14 TXER Ipd MII Transmit Error Input.
15 TXC/ I/O MII Transmit Clock Output.
REFCLK Input for crystal or an external 50MHz clock. When REFCLK pin is used for
REF clock interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave
XO pin unconnected.
16 TXEN Ipd MII Transmit Enable Input.
17 TXD0 Ipd MII Transmit Data Input.
18 TXD1 Ipd MII Transmit Data Input.
Notes:
1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

KSZ8721CL

Mfr. #:
Buy KSZ8721CL
Manufacturer:
Microchip Technology / Micrel
Description:
Ethernet ICs 10/100 BASE-TX/FX Physical Layer Transceiver
Lifecycle:
New from this manufacturer.
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