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PHD71NQ03LT,118

P1-P3P4-P6P7-P9P10-P12P13-P14
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
PHD71NQ03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 9 March 2010 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Simple gate drive required due to low
gate charge
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC convertors Switched-mode power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
V
DS
drain-source voltage T
j
≥ 25 °C; T
j
≤ 175 °C - - 30 V
I
D
drain current T
mb
=25°C; V
GS
=10V;
see Figure 1 and 3
--75A
P
tot
total power dissipation T
mb
= 25 °C; see Figure 2 - - 120 W
Dynamic characteristics
Q
GD
gate-drain charge V
GS
=5V; I
D
=50A;
V
DS
=15V; T
j
=25°C;
see Figure 11
-4.6-nC
Static characteristics
R
DSon
drain-source on-state
resistance
V
GS
=10V; I
D
=25A;
T
j
= 25 °C; see Figure 9
-810mΩ
PHD71NQ03LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 9 March 2010 2 of 13
NXP Semiconductors
PHD71NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
[1] It is not possible to make a connection to pin 2.
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1G gate
SOT428 (DPAK)
2D drain
[1]
3S source
mb D mounting base; connected to
drain
3
2
mb
1
S
D
G
m
bb076
Table 3. Ordering information
Type number Package
Name Description Version
PHD71NQ03LT DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
SOT428
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage T
j
≥ 25 °C; T
j
≤ 175 °C - 30 V
V
DGR
drain-gate voltage T
j
≥ 25 °C; T
j
≤ 175 °C; R
GS
=20kΩ -30V
V
GS
gate-source voltage -20 20 V
I
D
drain current V
GS
=10V; T
mb
= 100 °C; see Figure 1 -57.5A
V
GS
=10V; T
mb
=25°C; see Figure 1 and 3 -75A
I
DM
peak drain current t
p
≤ 10 µs; pulsed; T
mb
=25°C; see Figure 3 -240A
P
tot
total power dissipation T
mb
=25°C; see Figure 2 -120W
T
stg
storage temperature -55 175 °C
T
j
junction temperature -55 175 °C
V
GSM
peak gate-source
voltage
pulsed; δ =25%; t
p
≤ 50 µs -25 25 V
Source-drain diode
I
S
source current T
mb
=25°C - 75 A
I
SM
peak source current t
p
≤ 10 µs; pulsed; T
mb
=25°C - 57.7 A
P1-P3P4-P6P7-P9P10-P12P13-P14

PHD71NQ03LT,118

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Manufacturer:
Nexperia
Description:
MOSFET TAPE13 PWR-MOS
Lifecycle:
New from this manufacturer.
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