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PHD71NQ03LT,118

P1-P3P4-P6P7-P9P10-P12P13-P14
PHD71NQ03LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 9 March 2010 3 of 13
NXP Semiconductors
PHD71NQ03LT
N-channel TrenchMOS logic level FET
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
03ai74
0
40
80
120
0 50 100 150 200
T
mb
(
°
C)
I
der
(%)
T
mb
(°C)
0 20015050 100
03aa16
40
80
120
P
der
(%)
0
03ai76
1
10
10
2
10
3
1 10 10
2
V
DS
(V)
I
D
(A)
DC
10 ms
Limit R
DSon
= V
DS
/ I
D
1 ms
t
p
= 10 μs
100 μs
PHD71NQ03LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 9 March 2010 4 of 13
NXP Semiconductors
PHD71NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-mb)
thermal resistance from junction to
mounting base
see Figure 4 - - 1.25 K/W
R
th(j-a)
thermal resistance from junction to
ambient
mounted on a printed-circuit
board; minimum footprint
-75-K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
10-2
10-1
1
10
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
Z
th(j-mb)
(K/W)
single pulse
0.2
0.1
0.05
0.02
δ = 0.5
t
p
t
p
T
P
t
T
δ =
03ai75
PHD71NQ03LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 9 March 2010 5 of 13
NXP Semiconductors
PHD71NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V
(BR)DSS
drain-source
breakdown voltage
I
D
=250µA; V
GS
=0V; T
j
=-55°C 27 - - V
I
D
=250µA; V
GS
=0V; T
j
=25°C 30 - - V
V
GS(th)
gate-source threshold
voltage
I
D
=1mA; V
DS
= V
GS
; T
j
= 175 °C; see Figure 8 0.6 - - V
I
D
=1mA; V
DS
= V
GS
; T
j
=-55°C; see Figure 8 --2.9V
I
D
=1mA; V
DS
= V
GS
; T
j
=25°C; see Figure 8 11.92.5V
I
DSS
drain leakage current V
DS
=30V; V
GS
=0V; T
j
= 25 °C - 0.05 1 µA
V
DS
=30V; V
GS
=0V; T
j
=175°C - - 500 µA
I
GSS
gate leakage current V
GS
=20V; V
DS
=0V; T
j
= 25 °C - 10 100 nA
V
GS
=-20V; V
DS
=0V; T
j
= 25 °C - 10 100 nA
R
DSon
drain-source on-state
resistance
V
GS
=5V; I
D
=25A; T
j
= 175 °C; see Figure 9
and 10
- 21.6 27.4 mΩ
V
GS
=10V; I
D
=25A; T
j
=25°C; see Figure 9 -810mΩ
V
GS
=5V; I
D
=25A; T
j
=25°C; see Figure 9
and 10
-1215.2mΩ
Dynamic characteristics
Q
G(tot)
total gate charge I
D
=50A; V
DS
=15V; V
GS
=5V; T
j
=25°C;
see Figure 11
- 13.2 - nC
Q
GS
gate-source charge - 5.3 - nC
Q
GD
gate-drain charge - 4.6 - nC
C
iss
input capacitance V
DS
=25V; V
GS
= 0 V; f = 1 MHz; T
j
=25°C;
see Figure 12
- 1220 - pF
C
oss
output capacitance - 330 - pF
C
rss
reverse transfer
capacitance
- 140 - pF
t
d(on)
turn-on delay time V
DS
=15V; R
L
=0.6Ω; V
GS
=4.5V;
R
G(ext)
=5.6Ω; T
j
=25°C; I
D
=25A
-15-ns
t
r
rise time - 150 - ns
t
d(off)
turn-off delay time - 13.5 - ns
t
f
fall time - 18 - ns
Source-drain diode
V
SD
source-drain voltage I
S
=25A; V
GS
=0V; T
j
= 25 °C; see Figure 13 -0.91.2V
t
rr
reverse recovery time I
S
=10A; dI
S
/dt = -100 A/µs; V
GS
=0V;
V
DS
=25V; T
j
=25°C
-29-ns
Q
r
recovered charge - 20 - nC
P1-P3P4-P6P7-P9P10-P12P13-P14

PHD71NQ03LT,118

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Manufacturer:
Nexperia
Description:
MOSFET TAPE13 PWR-MOS
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