AD5378
Rev. A | Page 9 of 28
PARALLEL INTERFACE
V
CC
= 2.7 V to 5.5 V; V
DD
= 11.4 V to 16.5 V; V
SS
= −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; V
REF
(+) = +5 V;
V
REF
() = 3.5 V, FIFOEN = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 6.
Parameter
1, 2, 3
Limit at T
MIN
to T
MAX
Unit Description
t
0
4.5 ns min
REG0, REG1, Address to WR
Rising Edge Setup Time.
t
1
4.5 ns min
REG0, REG1, Address to WR
Rising Edge Hold Time.
t
2
10 ns min
CS
Pulse Width Low.
t
3
10 ns min
WR
Pulse Width Low.
t
4
0 ns min
CS
to WR Falling Edge Setup Time.
t
5
0 ns min
WR
to CS Rising Edge Hold Time.
t
6
4.5 ns min
Data to WR
Rising Edge Setup Time.
t
7
4.5 ns min
Data to WR
Rising Edge Hold Time.
t
8
20 ns min
WR
Pulse Width High.
t
9
240 ns min
Minimum WR
Cycle Time (Single-Channel Write).
t
10
4
0/30 ns min/max
WR
Rising Edge to BUSY Falling Edge.
t
11
4
330 ns max
BUSY
Pulse Width Low (Single-Channel Update). See Table 11.
t
12
0 ns min
BUSY
Rising Edge to WR Rising Edge.
t
13
30 ns min
WR
Rising Edge to LDAC Falling Edge.
t
14
20 ns min
LDAC
Pulse Width Low.
t
15
4
150 ns typ
BUSY
Rising Edge to DAC Output Response Time.
t
16
20 ns min
LDAC
Rising Edge to WR Rising Edge.
t
17
0 ns min
BUSY
Rising Edge to LDAC Falling Edge.
t
18
100 ns typ
LDAC
Falling Edge to DAC Output Response Time.
t
19
20/30 μs typ/ max DAC Output Settling Time.
t
20
10 ns min
CLR
Pulse Width Low.
t
21
350 ns max
CLR
/RESET Pulse Activation Time.
t
22
10 ns min
RESET
Pulse Width Low.
t
23
120 μs max
RESET
Time Indicated by BUSY Low.
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 6.
4
Measured with load circuit in Figure 2.
AD5378
Rev. A | Page 10 of 28
REG0,
REG1,
A7–A02
CS
WR
DB12–DB0
BUSY
LDAC
1
VOUT
1
LDAC
2
VOUT
2
CLR
VOUT
1
LDAC ACTIVE DURING BUSY.
2
LDAC ACTIVE AFTER BUSY.
RESET
VOUT
BUSY
t
0
t
1
t
4
t
5
t
2
t
3
t
9
t
8
t
6
t
7
t
16
t
10
t
11
t
13
t
14
t
12
t
15
t
19
t
14
t
18
t
20
t
21
t
22
t
21
t
23
t
19
t
17
05292-006
Figure 6. Parallel Interface Timing Diagram
AD5378
Rev. A | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 7.
Parameter Rating
V
DD
to AGND −0.3 V to +17 V
V
SS
to AGND −17 V to +0.3 V
V
CC
to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to V
CC
+ 0.3 V
Digital Outputs to DGND −0.3 V to V
CC
+ 0.3 V
V
REF
1(+), V
REF
2(+) to AGND −0.3 V to +7 V
V
REF
1(−), V
REF
2(−) to AGND V
SS
− 0.3 V to V
DD
+ 0.3 V
V
BIAS
to AGND −0.3 V to +7 V
VOUT0–VOUT31 to AGND V
SS
− 0.3 V to V
DD
+ 0.3 V
REFGND to AGND V
SS
− 0.3 V to V
DD
+ 0.3 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (T
A
)
Industrial (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (T
J
max) 150°C
108-Lead CSPBGA Package
θ
JA
Thermal Impedance 37.5°C/W
θ
JC
Thermal Impedance 8.5°C/W
Reflow Soldering
Peak Temperature 230°C
Time at Peak Temperature 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD5378ABCZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 32-CH 14BIT BIPOLAR VOUT IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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