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AD5378ABCZ

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AD5378
Rev. A | Page 21 of 28
FIFO VS. NON-FIFO OPERATION
Data can be loaded to the AD5378 registers with FIFO disabled
or enabled. Operation with FIFO disabled is optimum for single
writes to the device. If the system requires significant data
transfers to the AD5378, however, operation with FIFO enabled
is more efficient.
When FIFO is enabled, the AD5378 uses an internal FIFO
memory to allow high speed successive writes in both serial and
parallel modes. This optimizes the interface speed and
efficiency, minimizes the total conversion time due to internal
digital efficiencies, and minimizes the overhead on the master
controller when managing the data transfers. The BUSY signal
goes low while instructions in the state machine are being
executed.
Table 11 compares operation with FIFO enabled and FIFO
disabled for different data transfers to the AD5378. Operation
with FIFO enabled is more efficient for all operations except
single write operations. When using the FIFO, the user can
continue writing new data to the AD5378 while write instruc-
tions are being executed. Up to 128 successive instructions can
be written to the FIFO at maximum speed. When the FIFO is
full, additional writes to the AD5378 are ignored.
BUSY INPUT FUNCTION
Because the
BUSY
pin is bidirectional and open-drain (for
correct operation, use a pull-up resistor to digital supply), a
second AD5378 or any other device (such as a system control-
ler), can pull
BUSY
low and, therefore, delay DAC update(s), if
required. This is a means of delaying any
LDAC
action. This
feature allows synchronous updates of multiple AD5378 devices
in a system at maximum speed. As soon as the last device
connected to the
BUSY
pin is ready, all DACs update automati-
cally. Tying the
BUSY
pin of multiple devices together enables
synchronous updating of all DACs without extra hardware.
POWER-ON RESET FUNCTION
The AD5378 contains a power-on reset generator and state
machine. During power-on,
CLR
becomes active (internally),
the power-on state machine resets all internal registers to their
default values, and
BUSY
goes low. This sequence takes 8 ms
(typical). The outputs, VOUT0 to VOUT31, are switched to the
externally set potential on the REFGND pin. During power-on,
the parallel interface is disabled, so it is not possible to write to
the part. Any transitions on
LDAC
during the power-on period
are ignored in order to reject initial
LDAC
pin glitching. A
rising edge on
BUSY
indicates that power-on is complete and
that the parallel interface is enabled. All DACs remain in their
power-on state until
LDAC
is used to update the DAC outputs.
RESET INPUT FUNCTION
The AD5378 can be placed into the power-on reset state at any
time by activating the
RESET
pin. The AD5378 state machine
initiates a reset sequence to digitally reset the x1, m, c, and x2
registers to their default power-on values. This sequence takes
95 μs (typical), 120 μs (max), and 70 μs (min). During this
sequence,
BUSY
goes low. While
RESET
is low, any transitions
on
LDAC
are ignored. As with the
CLR
input, while
RESET
is
low, the DAC outputs are switched to REFGND. The outputs
remain at REFGND until an
LDAC
pulse is applied. This reset
function can also be implemented via the parallel interface by
setting the REG0 and REG1 pins low and writing all 1s to DB13
to DB0. See Table 17 for soft reset.
INCREMENT/DECREMENT FUNCTION
The AD5378 has a special function register that enables the user
to increment or decrement the internal 14-bit input register
data (x1) in steps of 0 to 127 LSBs. The increment/decrement
function is selected by setting both REG1 and REG0 pins (or
bits) low. Address Pins (or bits) A7 to A0 are used to select a
DAC channel or group of channels. The amount by which the
x1 register is incremented or decremented is determined by the
DB6 to DB0 bits/pins. For example, for a 1 LSB increment or
decrement, DB6...DB0 = 0000001, while for a 7 LSB increment
or decrement, DB6...DB0 = 0000111. DB8 determines whether
the input register data is incremented (DB8 = 1) or decre-
mented (DB8 = 0). The maximum amount by which the user is
allowed to increment or decrement the data is 127 LSBs, that is,
DB6...DB0 = 1111111. The 0 LSB step is included to facilitate
software loops in the user’s application. See Table 16.
The AD5378 has digital overflow and underflow detection
circuitry to clamp at full scale or zero scale when the values
chosen for increment or decrement mode are out of range.
AD5378
Rev. A | Page 22 of 28
INTERFACES
The AD5378 contains parallel and serial interfaces. The active
interface is selected via the SER/
PAR
pin.
The AD5378 uses an internal FIFO memory to allow high
speed successive writes in both serial and parallel modes. The
user can continue writing new data to the AD5378 while write
instructions are being executed. The
BUSY
signal goes low
while instructions in the FIFO are being executed. Up to
120 successive instructions can be written to the FIFO at
maximum speed. When the FIFO is full, additional writes to the
AD5378 are ignored.
To minimize both the power consumption of the device and
on-chip digital noise, the active interface powers up fully only
when the device is being written to, that is, on the falling edge
of
WR
or on the falling edge of
SYNC
.
All digital interfaces are 2.5 V LVTTL-compatible when
operating from a 2.7 V to 3.6 V V
CC
supply.
PARALLEL INTERFACE
A pull-down on the SER/
PAR
pin makes the parallel interface
the default. If using the parallel interface, the SER/
PAR
pin can
be left unconnected. Figure 6 shows the timing diagram for a
parallel write to the AD5378. The parallel interface is controlled
by the following pins.
CS
Pin
Active low device select pin.
WR
Pin
On the rising edge of
WR
, with
CS
low, the address values at
Pins A7 to A0 are latched and data values at Pins DB13 to DB0
are loaded into the selected AD5378 input registers.
REG1, REG0 Pins
The REG1 and REG0 pins determine the destination register of
the data being written to the AD5378. See Table 12.
Table 12. Register Selection
REG1 REG0 Register Selected
1 1 Input Data Register (x1)
1 0 Offset Register (c)
0 1 Gain Register (m)
0 0 Special Function Register
DB13 to DB0 Pins
The AD5378 accepts a straight 14-bit parallel word on DB0 to
DB13, where DB13 is the MSB and DB0 is the LSB. See Table 13
to Table 17.
A7 to A0 Pins
Each of the 32 DAC channels can be addressed individually. In
addition, several channel groupings enable the user to simulta-
neously write the same data to multiple DAC channels. Address
Bits A7 to A4 are decoded to select one group or multiple
groups of registers. Address Bits A3 to A0 select one of ten
input data registers (x1), offset registers (c), or gain registers
(m). See Table 18.
SERIAL INTERFACE
The SER/
PAR
pin must be tied high to enable the serial inter-
face and disable the parallel interface. The serial interface is
controlled by the following pins.
SYNC
, DIN, SCLK
Standard 3-wire interface pins.
DCEN
Selects standalone mode or daisy-chain mode.
SDO
Data out pin for daisy-chain mode.
Figure 4 and Figure 5 show the timing diagrams for a serial
write to the AD5378 in standalone and daisy-chain modes,
respectively.
The 24-bit data-word format for the serial interface is shown in
Figure 21.
MSB
REG0 DB13–DB0
LSB
A7–A0 REG1
REGISTER DATA BITS
GROUP/CHANNEL
SELECT BITS
REGISTER SELECT
BITS
05292-021
Figure 21. Serial Data Format
Standalone Mode
By connecting the DCEN (daisy-chain enable) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a burst serial clock. The first falling edge
of
SYNC
starts the write cycle and resets a counter that counts
the number of serial clocks to ensure that the correct number of
bits is shifted into the serial shift register. Additional edges on
SYNC
are ignored until 24 bits are shifted in. Once 24 bits are
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
SYNC
.
AD5378
Rev. A | Page 23 of 28
Daisy-Chain Mode
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
Connecting the DCEN (daisy-chain enable) pin high enables
daisy-chain mode. The first falling edge of
SYNC
starts the
write cycle. The SCLK is continuously applied to the input shift
register when
SYNC
is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting this line to
the DIN input on the next device in the chain, a multidevice
interface is constructed. For each AD5378 in the system,
24 clock pulses are required. Therefore, the total number of
clock cycles must equal 24N, where N is the total number of
AD5378 devices in the chain. If fewer than 24 clocks are
applied, the write sequence is ignored.
When the serial transfer to all devices is complete,
SYNC
should be taken high. This latches the input data in each device
in the daisy chain and prevents any additional data from being
clocked into the input shift register.
A continuous SCLK source can be used if
SYNC
is held low for
the correct number of clock cycles. Alternatively, a burst clock
containing the exact number of clock cycles can be used and
SYNC
taken high after the final clock to latch the data.
When the transfer to all input registers is complete, a common
LDAC
signal updates all DAC registers, and all analog outputs
are updated simultaneously.
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AD5378ABCZ

Mfr. #:
Buy AD5378ABCZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 32-CH 14BIT BIPOLAR VOUT IC
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New from this manufacturer.
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