LTC4222
17
4222fb
APPLICATIONS INFORMATION
Fault Alerts
When any of the fault bits in a FAULT register (see Table 4)
are set, an optional bus alert is generated if the appropri-
ate bit in the ALERT register has been set. This allows
only selected faults to generate alerts. At power-up the
default state is to not alert on faults and the ALERT pin
is high. If an alert is enabled, the corresponding fault
causes the ALERT pin to pull low. After the bus master
controller broadcasts the Alert Response Address, the
LTC4222 responds with its address on the SDA line and
releases ALERT as shown in Table 7. If there is a collision
between two LTC4222s responding with their addresses
simultaneously, then the device with the lower address
wins arbitration and responds first. The ALERT line is also
released if the device is addressed by the bus master if
ALERT is pulled low due to an alert.
Once the ALERT signal has been released for one fault, it
is not pulled low again until the FAULT register indicates a
different fault has occurred or the original fault is cleared
and it occurs again. Note that this means repeated or
continuing faults do not generate alerts until the associ-
ated FAULT register bit has been cleared.
Resetting Faults
Faults are reset with any of the following conditions on a
given channel. First, a serial bus command writing zeros
to the FAULT register bits 0 to 5 clears the associated
faults. Second, FAULT register bits 0 to 5 are cleared when
the corresponding switch is turned off by the ON pin or
STATUS bit 3 going from high to low, if the corresponding
UV pin is brought below its 0.4V reset threshold for 2µs,
or if INTV
CC
falls below its 2.64V undervoltage lockout
threshold. Finally, when EN is brought from high to low,
only corresponding FAULT bits 0-3 and 5 are cleared, and
bit 4, which indicates a EN change of state, is set. Note
that faults that are still present, as indicated in the STATUS
registers, cannot be cleared.
The FAULT registers are not cleared when auto-retrying.
When auto-retry is disabled the existence of an overvoltage,
undervoltage, or overcurrent fault keeps the switch off.
As soon as the fault is cleared, the switch turns on. If
auto-retry is enabled, then a high value in STATUS register
bits 0 or 1 holds the switch off and the fault register is
ignored. Subsequently, when STATUS register bits 0 and
1 are cleared by removal of the fault condition, the switch
is allowed to turn on again. The LTC4222 will set FAULT
bit 2 and turn off in the event of an overcurrent fault,
preventing it from remaining in an overcurrent condition.
If configured to auto-retry, the LTC4222 will continually
attempt to restart after cool-down cycles until it succeeds
in starting up without generating an overcurrent fault. Note
that if a switch is on after an auto-retry and the FAULT bit
has not been reset, clearing the corresponding auto-retry
bit will turn the channel off.
Data Converter
The LTC4222 incorporates a 10-bit A/D converter that
continuously scans six different voltages. The SOURCE
pins have a 1/24 resistive divider to monitor a full-scale
voltage of 32V with 31.25mV resolution. The ADIN pins are
monitored with a 1.28V full scale and 1.25mV resolution,
and the voltage between the V
DD
and SENSE pins is moni-
tored with a 64mV full scale and 62.5µV resolution.
Results from each conversion are stored, left justified, in
registers as seen in Tables 7 and 8, and are updated 15
times per second. Setting ADC_CONTROL register bit 0
invokes a test mode that halts the data converter so that
the data converter result registers may be written to and
read from for software testing.
The data converter also has a direct address mode that
allows the user to take a specific measurement at a spe-
cific time and hold that value for later readback. Direct
address mode is entered by setting the Halt bit, bit 0, in
the ADC_CONTROL register (see Table 9). Then when
the channel address bits, ADC_CONTROL bits 1 to 3, are
written to, the ADC will make a single measurement on
the channel indicated by those bits, then stop. Setting the
ADC Alert bit, ADC_CONTROL bit 4, will enable an interrupt
when the data converter finishes the conversion, result-
ing in the ALERT pin pulling low when the data is ready.
Alternately, the ADC Busy bit, ADC_CONTROL bit 5, can
be polled to check for the end of the conversion, after a
direct address conversion the ADC Busy bit will go low. In
normal mode ADC Busy is always high. Resetting the Halt
bit returns the data converter to the scan mode.
