Document Number: 001-10261 Rev. *H Page 4 of 10
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
V
DD
Supply voltage –0.5 4.4 V
V
IN
[1]
Input voltage, DC Relative to V
SS
–0.5 V
DD
+ 0.5 V
T
S
Temperature, storage Non operating –55 135 °C
T
J
Temperature, junction –40 135 °C
ESD
HBM
Electrostatic discharge (ESD) protection
human body model (HBM)
JEDEC Std 22-A114-B 2000 – V
JA
[2]
Thermal resistance, junction to ambient 0 m/s airflow 64 °C / W
Operating Conditions
Parameter Description Min Typ Max Unit
V
DD
3.3 V supply voltage range 3.0 3.3 3.6 V
2.5 V supply voltage range 2.375 2.5 2.625 V
T
PU
Power-up time for V
DD
to reach minimum specified voltage (power ramp is
monotonic)
0.05 – 500 ms
T
A
Ambient temperature (commercial) 0 – 70 °C
Ambient temperature (industrial) –40 – 85 °C
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. I
DD
includes ~4 mA of current that is dissipated externally in the output termination resistors.
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
I
DD
[3]
Operating supply current V
DD
= 3.6 V, OE/PD# = V
DD
,
output terminated
– – 125 mA
V
DD
= 2.625 V, OE/PD# = V
DD
,
output terminated
– – 120 mA
I
SB
Standby supply current PD# = V
SS
– – 200 A
V
OD
LVDS differential output voltage V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100 between CLK and
CLK#
247 – 454 mV
V
OD
Change in V
OD
between complementary
output states
V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100 between CLK and
CLK#
––50mV
V
OS
LVDS offset output voltage V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100 between CLK and
CLK#
1.125 – 1.375 V
V
OS
Change in V
OS
between complementary
output states
V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100 between CLK and
CLK#
––50mV
I
OZ
LVDS output leakage current Tri-state output, unterminated,
measured on one pin while floating
the other pin, PD#/OE = V
SS
–35 – 35 A
V
IH
Input high voltage 0.7 × V
DD
–– V
V
IL
Input low voltage – – 0.3 × V
DD
V
I
IH
Input high current Input = V
DD
––115A
I
IL
Input low current Input = V
SS
––50A
C
IN
[3]
Input capacitance, OE/PD# pin – 15 – pF
