PIN # PIN NAME PIN TYPE DESCRIPTION
1 PLL_BW IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2 CLK_INT IN True Input for differential reference clock.
3 CLK_INC IN Complementary Input for differential reference clock.
4 vCLKREQ1# IN
Output enable for PCI Express output pair 1.
0 = enabled, 1 =disabled
5 PCIEXT0 OUT True clock of differential PCI_Express pair.
6 PCIEXC0 OUT Complementary clock of differential PCI_Express pair.
7 VDD PWR Power supply, nominal 3.3V
8 GND IN Ground pin.
9 PCIEXT1 OUT True clock of differential PCI_Express pair.
10 PCIEXC1 OUT Complementary clock of differential PCI_Express pair.
11 PCIEXT2 OUT True clock of differential PCI_Express pair.
12 PCIEXC2 OUT Complementary clock of differential PCI_Express pair.
13 VDD PWR Power supply, nominal 3.3V
14 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
15 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
16 VDD PWR Power supply, nominal 3.3V
17 PCIEXC3 OUT Complementary clock of differential PCI_Express pair.
18 PCIEXT3 OUT True clock of differential PCI_Express pair.
19 PCIEXC4 OUT Complementary clock of differential PCI_Express pair.
20 PCIEXT4 OUT True clock of differential PCI_Express pair.
21 GND PWR Ground pin.
22 VDD PWR Power supply, nominal 3.3V
23 PCIEXC5 OUT Complementary clock of differential PCI_Express pair.
24 PCIEXT5 OUT True clock of differential PCI_Express pair.
25 vCLKREQ4# IN
Output enable for PCI Express output pair 4.
0 = enabled, 1 =disabled
26 IREF OUT
output pairs. It requires a fixed precision resistor to ground.
475ohm is the standard value for 100ohm differential impedance.
Other impedances require different values. See data sheet.
27 GNDA PWR Ground pin for the PLL core.
28 VDDA PWR 3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
