IDT
®
Six Output Differential Buffer for PCIe Gen 2 9DB106 REV L 05/24/12
9DB106
Six Output Differential Buffer for PCIe Gen 2
5
Electrical Characteristics - Clock Input Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage -
DIF_IN
V
IHDIF
Differential inputs
(single-ended measurement)
600 800 1150 mV 1
Input Low Voltage -
DIF_IN
V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential
wavefrom
45 55 % 1
Input Jitter - Cycle to
Cycle
J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - PLL Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PLL Jitter Peaking j
peak-hibw
(PLL_BW = 1) 0 1 2.5 dB 1,4
PLL Jitter Peaking j
peak-lobw
(PLL_BW = 0) 0 1 2 dB 1,4
PLL Bandwidth pll
(PLL_BW = 1) 2 2.5 3 MHz 1,5
PLL Bandwidth pll
(PLL_BW = 0) 0.4 0.5 1 MHz 1,5
PCIe Gen 1 phase jitter
40 108 ps 1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
2.7 3.1 ps rms 1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
2.2 3.1 ps rms 1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
1.3 3 ps rms 1,2,3
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4.
Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5.
Measured at 3 db dow n or half pow er point.
Jitter, Phase t
jphasePLL
