9DB106
Six Output Differential Buffer for PCIe Gen 2
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Printed in USA
Revision History
Rev. Originator Issue Date Description Page #
B RDW 9/12/2005
1. Changed Output to Output skew from 30ps to 45ps.
2. Changed PLL mode jitter from 40ps to 35ps.
3. Changed Bypass mode additive jitter from 25ps to 35ps.
4. Updated LF Ordering Information.
5,
8-9
C RDW 8/17/2006
Corrected Typo of SMBus Read/Write Address.
7
D RDW 3/12/2007
Added SMBus Read/Write Table.
6
E RDW 8/6/2007
1. Added Phase Noise Parameters, Updated input to output delay values.
2. PLL BW moved to PLL parameters table.
3. Added terminations tables. 6-8
F 12/14/2007 Updated SMBus serial Interface Information. 9
G RDW 4/1/2010 Updated ordering info for Rev B 13
H RDW 9/15/2010
1. Updated DS to include I-temp specs and ordering information
2. Updated electrical tables to reflect common set of numbers for I-temp and C-temp
3. Converted all references of ICS to IDT
4. Corrected placement of AC coupling caps in Figure 4
J RDW 1/27/2011 Updated Termination Figure 4. 8
K RDW 4/20/2011 1. Changed pull down indicator from '**" to " v " to correct pin description of CLKREQ# pins.
L AT 5/24/2012 Added OE# Latency spec to Common Input/Output Parameters table 4
