DS2417
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
PUP
= external pullup voltage.
4. Input load is to ground.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 µs of this falling edge.
6. Under certain low voltage conditions V
IL1MAX
may have to be reduced to as much as 0.5V to always
guarantee a presence pulse.
7. The reset low time (t
RSTL
) should be restricted to a maximum of 960µs, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
8. When V
DD
ramps up, the oscillator is always off.
9. At V
DD
= 3V ± 10%
10. At V
DD
= 5V ± 10%
11. V
IH1
has to be V
DD
– 0.3V or higher.
12. The optimal sampling point for the master is as close as possible to the end time of the 15μs t
RDV
period without exceeding t
RDV
. For the case of a Read-One Time Slot, this maximizes the amount of
time for the pull-up resistor to recover to a high level. For a Read-Zero Time Slot, it ensures that a
read will occur before the fastest 1-Wire device(s) release the line.
13. The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
6 TSOC D6+1 21-0382
6 Flip Chip BF611-2 21-0289
15
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Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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2007 Maxim Integrated
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