DS2417
Bit 4 - 6
IS Interval Select
These bits determine the time between interrupt pulses. The values available are shown below.
IS2 IS1 IS0 Interrupt Interval
0 0 0 1s
0 0 1 4s
0 1 0 32s = 0.53 min.
0 1 1 64s = 1.07 min.
1 0 0 2048s = 34.13 min.
1 0 1 4096s = 68.27 min.
1 1 0 65536s = 18.20 hours
1 1 1 131072s = 36.41 hours
Bit 7
IE Interrupt Enable
This bit controls whether the interrupt pulse will be generated at the selected interval. To enable
interrupts this bit needs to be 1.
REAL-TIME CLOCK
The real-time clock is a 32-bit binary counter. It is incremented once per second. The real-time clock
can accumulate 136 years of seconds before rolling over. Time/date is represented by the number of
seconds since a reference point, which is determined by the user. For example, 12:00 a.m., January 1,
1970 could be a reference point.
CLOCK FUNCTION COMMANDS
The “Clock Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the real-time
clock. With only four bytes of real-time clock and one control byte the DS2417 does not provide random
access. Reading and writing always starts with the device control byte followed by the least significant
byte of the time data.
READ CLOCK [66h]
The read clock command is used to read the device control byte and the contents of the real-time clock
counter. After having received the most significant bit of the command code the device copies the actual
contents of the real-time clock counter to the read/write buffer. Now, the bus master reads data beginning
with the device control byte followed by the least significant byte through the most significant byte of the
real-time clock. After this the bus master may continue reading from the DS2417. The data received will
be the same as in the first pass through the command flow. The read clock command can be ended at any
point by issuing a Reset Pulse.
WRITE CLOCK [99h]
The write clock command is used to set the real-time clock counter and to write the device control byte.
After issuing the command, the bus master writes first the device control byte, which becomes immedi-
ately effective. After this the bus master sends the least significant byte through the most significant byte
to be written to the real-time clock counter. The new time data is copied from the read/write buffer to the
real-time clock counter and becomes effective as the bus master generates a reset pulse. If enabled, an
interrupt pulse will be generated either immediately or delayed, depending on the actual time and the se-
lected interval duration (see Figure 11). If the oscillator is intentionally stopped the real-time clock
counter behaves as a four-byte nonvolatile memory.
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