DS2417
HARDWARE CONFIGURATION Figure 6
RX
TX
Open Drain
Port Pin
5 µA
Typ.
DS2417 1-WIRE PORT
RX = RECEIVE
TX = TRANSMIT
BUS MASTER
V
PUP
DATA
RX
TX
MOSFET
100
5 k
Typ.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the
DS2417 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire input of the DS2417 is open drain with an internal circuit equivalent
to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The
1-Wire bus has a maximum data rate of 16.3kbits per second and requires a pullup resistor of approxi-
mately 5k.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120s, one or more of the devices on the bus may be reset. Since the DS2417 gets all its
energy for operation through its V
DD
pin it will NOT perform a power-on reset if the 1-Wire bus is low
for an extended time period.
TRANSACTION SEQUENCE
The protocol for accessing the DS2417 via the 1-Wire port is as follows:
Initialization
ROM Function Command
Clock Function Command
7 of 15
DS2417
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence con-
sists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2417 is on the bus and is ready to
operate. For more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands that
the DS2417 supports. All ROM function commands are eight bits long. A list of these commands
follows (refer to flowchart in Figure 7):
Read ROM [33h]
This command allows the bus master to read the DS2417’s 8-bit family code, unique 48-bit serial num-
ber, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more than
one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time
(open drain will produce a wired-AND result). The resultant family code and 48-bit serial number read
by the master will be invalid.
Match ROM [55h]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a spe-
cific DS2417 on a multidrop bus. Only the DS2417 that exactly matches the 64-bit ROM sequence will
respond to the following clock function command. All slaves that do not match the 64-bit ROM
sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the
bus.
SEARCH ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the de-
sired value of that bit. The bus master performs this three-step routine on each bit of the ROM. After one
complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify
the ROM codes of the remaining devices. See Application Note 187 for a comprehensive discussion of a
search ROM, including an actual example.
Skip ROM [CCh]
This command can save time in a single drop bus system by allowing the bus master to access the clock
functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for
example, a read command is issued following the Skip ROM command, data collision will occur on the
bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result).
8 of 15
DS2417
9 of 15
ROM FUNCTIONS FLOW CHART Figure 7
F0H
Search ROM
Command
?
DS2417 TX Bit 0
DS2417 TX Bit 0
Master TX Bit 0
Bit 0
Match ?
DS2417 TX Bit 1
DS2417 TX Bit 1
Master TX Bit 1
Bit 1
Match ?
DS2417 TX Bit 63
DS2417 TX Bit 63
Master TX Bit 63
Bit 63
Match ?
Master TX Control
Function Command
33H
Read ROM
Command
?
DS2417 TX
Serial Number
6 Bytes
DS2417 TX
CRC Byte
DS2417 TX
Family Code
1 Byte
Match ROM
55H
Command
?
Bit 0
Match ?
Bit 1
Match ?
Bit 63
Match ?
Master TX Bit 1
Master TX Bit 0
N
Y
N
Y
NN
Y
NN
NN
Y
Y
Y
Y
Y
Y
(
SEE FIGURE 5
)
Master TX ROM
Function Command
Master TX
Reset Pulse
DS2417 TX
Presence Pulse
CCH
Skip ROM
Command
?
N
Y
N
Master TX Bit 63

DS2417P

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IC RTC BINARY CNT SER 6-TSOC
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