AD7676ASTZ Datasheet AD7676ASTZ, AD7676ASTZRL | P13-P15

REV. B

AD7676

–12–

During the acquisition phase for ac signals, the AD7676 behaves

like a one-pole RC filter consisting of the equivalent resistance

R+, R–,

and C

. The resistors R+ and R– are typically 684 Ω and

are lumped components made up of some serial resistors and the

on resistance of the switches. The capacitor C

is typically 60 pF

and is mainly the ADC sampling capacitor. This one-pole filter

with a typical –3 dB cutoff frequency of 3.88 MHz reduces unde-

sirable aliasing effects and limits the noise coming from the inputs.

Because the input impedance of the AD7676 is very high, the

AD7676 can be driven directly by a low impedance source without

gain error. That allows users to put, as shown in Figure 5, an

external one-pole RC filter between the output of the amplifier

output and the ADC analog inputs to even further improve the

noise filtering done by the AD7676 analog input circuit. However,

the source impedance has to be kept low because it affects the

ac performances, especially the total harmonic distortion (THD).

The maximum source impedance depends on the amount of

THD that can be tolerated. The THD degrades proportionally

to the source impedance.

Single-to-Differential Driver

For applications using unipolar analog signals, a single-ended-to-

differential driver will allow for a differential input into the part.

The schematic is shown in Figure 8.

590

2.5V REF

AD8021

590

AD7676

IN+

IN–

REF

2.5V REF

ANALOG INPUT

(UNIPOLAR)

AD8021

590

Figure 8. Single-Ended-to-Differential Driver Circuit

This configuration, when provided an input signal of 0 to V

REF

will produce a differential ±2.5 V with a common mode at 1.25 V.

If the application can tolerate more noise, the AD8138 can be used.

Driver Amplifier Choice

Although the AD7676 is easy to drive, the driver amplifier needs

to meet the following requirements:

• The driver amplifier and the AD7676 analog input circuit have

to be able, together, to settle for a full-scale step of the capaci-

tor array at a 16-bit level (0.0015%). In the amplifier’s data

sheet, the settling at 0.1% or 0.01% is more commonly

specified. It could significantly differ from the settling time

at the 16-bit level and, therefore, it should be verified prior to

the driver selection. The tiny op amp AD8021, which com-

bines ultralow noise and a high gain bandwidth, meets this

settling time requirement even when used with a high gain

up to 13.

• The driver needs to have a THD performance suitable to

that of the AD7676.

• The noise generated by the driver amplifier needs to be kept

as low as possible to preserve the SNR and transition noise

performance of the AD7676. The noise coming from the driver is

filtered by the AD7676 analog input circuit one-pole, low-pass

filter made by R+, R–, and C

. The SNR degradation due to

the amplifier is:

SNR LOG

fNe

LOSS













−

784

()

where:

–3 dB

is the –3 dB input bandwidth of the AD7676 (3.9 MHz)

or the cutoff frequency of the input filter if any is used.

N is the noise factor of the amplifier (1 if in buffer

configuration).

is the equivalent input noise voltage of the op amp in nV/√Hz .

For instance, a driver with an equivalent input noise of

2 nV/√Hz like the AD8021 and configured as a buffer, thus

with a noise gain of +1, will degrade the SNR by only 0.26 dB.

The AD8021 meets these requirements and is usually appropriate

for almost all applications. The AD8021 needs an external

compensation capacitor of 10 pF. This capacitor should have

good linearity as an NPO ceramic or mica type.

The AD8022 could also be used where a dual version is needed

and a gain of 1 is used.

The AD8132 or the AD8138 could also be used to generate

a differential signal from a single-ended signal.

The AD829 is another alternative where high frequency (above

500 kHz) performance is not required. In a gain of 1, it requires

an 82 pF compensation capacitor.

The AD8610 is also another option where low bias current is

needed in low frequency applications.

Voltage Reference Input

The AD7676 uses an external 2.5 V voltage reference.

The voltage reference input REF of the AD7676 has a dynamic

input impedance. Therefore, it should be driven by a low imped-

ance source with an efficient decoupling between the REF and

REFGND inputs. This decoupling depends on the choice of the

voltage reference but usually consists of a low ESR tantalum

capacitor connected to the REF and REFGND inputs with

minimum parasitic inductance. 47 µF is an appropriate value for

the tantalum capacitor when used with one of the recommended

reference voltages:

•

The low noise, low temperature drift ADR421 and AD780

voltage references

•

The low power ADR291 voltage reference

•

The low cost AD1582 voltage reference

For applications using multiple AD7676s, it is more effective to

buffer the reference voltage with a low noise, very stable op amp

like the AD8031.

Care should also be taken with the reference temperature coeffi-

cient of the voltage reference, which directly affects the full-scale

accuracy if this parameter matters. For instance, a ±15 ppm/°C

tempco of the reference changes the full scale by ±1 LSB/°C.

REV. B

AD7676

–13–

REF

, as mentioned in the specification table, could be increased

to AVDD – 1.85 V. The benefit here is the increased SNR obtained

as a result of this increase. Since the input range is defined in

terms of V

REF

, this would essentially increase the range to make

it a ±3 V input range with an AVDD above 4.85 V. The theo-

retical improvement as a result of this increase in reference is

1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise,

however, the observed improvement is approximately 1 dB. The

AD780 can be selected with a 3 V reference voltage.

Power Supply

The AD7676 uses three sets of power supply pins: an analog 5 V

supply AVDD, a digital 5 V core supply DVDD, and a digital

input/output interface supply OVDD. The OVDD supply allows

direct interface with any logic working between 2.7 V and

DVDD + 0.3 V. To reduce the number of supplies needed, the

digital core (DVDD) can be supplied through a simple RC filter

from the analog supply as shown in Figure 5. The AD7676 is

independent of power supply sequencing once OVDD does not

exceed DVDD by more than 0.3 V and thus free from supply

voltage-induced latch-up. Additionally, it is very insensitive to

power supply variations over a wide frequency range, as shown in

Figure 9.

FREQUENCY – Hz

PSRR – dB

10k 10M1k 1M

100k

Figure 9. PSRR vs. Frequency

POWER DISSIPATION

The AD7676 automatically reduces its power consumption at

the end of each conversion phase. During the acquisition phase,

the operating currents are very low, which allows a significant

power savings when the conversion rate is reduced, as shown in

Figure 10. This feature makes the AD7676 ideal for very low

power battery-operated applications.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital

supply currents even further, the digital inputs need to be driven

close to the power rails (i.e., DVDD and DGND) and OVDD

should not exceed DVDD by more than 0.3 V.

SAMPLING RATE – SPS

POWER DISSIPATION – W

0.1

10k

100 100k10 10k

100

100k

Figure 10. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conversion

process. The AD7676 is controlled by the signal CNVST, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conversion

is complete. The CNVST signal operates independently of CS

and RD signals.

CNVST

MODE

ACQUIRE CONVERT

ACQUIRE

CONVERT

BUSY

Figure 11. Basic Conversion Timing

For true sampling applications, the recommended operation of

the CNVST signal is the following:

CNVST must be held HIGH from the previous falling edge of

BUSY, and during a minimum delay corresponding to the acqui-

sition time t

; then, when CNVST is brought LOW, a conversion

is initiated and the BUSY signal goes HIGH until the comple-

tion of the conversion. Although CNVST is a digital signal, it

should be designed with this special care with fast, clean edges,

and levels, with minimum overshoot and undershoot or ringing.

For applications where the SNR is critical, the CNVST signal

should have a very low jitter. To achieve this, some use a dedicated

oscillator for CNVST generation or, at least, to clock it with a

high frequency low jitter clock as shown in Figure 5.

REV. B

AD7676

–14–

RESET

DATABUS

BUSY

CNVST

Figure 12. RESET Timing

For other applications, conversions can be automatically initiated.

If CNVST is held LOW when BUSY is LOW, the AD7676

controls the acquisition phase and then automatically initiates a

new conversion. By keeping CNVST LOW, the AD7676 keeps

the conversion process running by itself. It should be noted that

the analog input has to be settled when BUSY goes LOW. Also,

at power-up, CNVST should be brought LOW once to initiate the

conversion process. In this mode, the AD7676 could sometimes

run slightly faster than the guaranteed limit of 500 kSPS.

DIGITAL INTERFACE

The AD7676 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel databus. The

AD7676 digital interface also accommodates both 3 V or 5 V

logic by simply connecting the OVDD supply pin of the AD7676

to the host system interface digital supply. Finally, by using the

OB/2C input pin, either twos complement or straight binary

coding can be used.

The two signals CS and RD control the interface. When at least

one of these signals is HIGH, the interface outputs are in high

impedance. Usually, CS allows the selection of each AD7676 in

multicircuit applications and is held LOW in a single AD7676

design. RD is generally used to enable the conversion result on

the databus.

CNVST

BUSY

DATABUS

CS = RD = 0

PREVIOUS CONVERSION DATA NEW DATA

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7676 is configured to use the parallel interface (Figure 13)

when the SER/PAR is held LOW. The data can be read either

after each conversion, which is during the next acquisition phase,

or during the following conversion as shown, respectively, in

Figures 14 and 15. When the data is read during the conversion,

however, it is recommended that it be read-only during the first

half of the conversion phase. That avoids any potential feedthrough

between voltage transients on the digital interface and the most

critical analog conversion circuitry.

DATABUS

BUSY

CURRENT

CONVERSION

Figure 14. Slave Parallel Data Timing for Reading

(Read after Conversion)

CS = 0

CNVST,

CONVERSION

DATABUS

BUSY

Figure 15. Slave Parallel Data Timing for Reading (Read

during Conversion)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 16, the LSB byte is output on D[7:0] and the

MSB is output on D[15:8] when BYTESWAP is LOW. When

BYTESWAP is HIGH, the LSB and MSB bytes are swapped and

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16-bit data

can be read in two bytes on either D[15:8] or D[7:0].

BYTE

PINS D[15:8]

PINS D[7:0]

HI-Z

HIGH BYTE LOW BYTE

LOW BYTE HIGH BYTE

HI-Z

Figure 16. 8-Bit Parallel Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7676ASTZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 500kSPS CMOS 16-Bit w/ INL of 1 LSB Max

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AD7676ASTZ

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