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AD7676ASTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
REV. B
–3–
AD7676
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
Refer to Figures 11 and 12
Convert Pulsewidth t
1
5ns
Time between Conversions t
2
2 µs
CNVST LOW to BUSY HIGH Delay t
3
30 ns
BUSY HIGH All Modes except in Master Serial Read t
4
1.25 µs
Convert Mode
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
1.25 µs
Acquisition Time t
8
750 ns
RESET Pulsewidth t
9
10 ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
1.25 ns
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
Refer to Figures 16 and 17 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay t
17
525 ns
SYNC Asserted to SCLK First Edge Delay
2
t
18
3ns
Internal SCLK Period
2
t
19
25 40 ns
Internal SCLK HIGH
2
t
20
12 ns
Internal SCLK LOW
2
t
21
7ns
SDOUT Valid Setup Time
2
t
22
4ns
SDOUT Valid Hold Time
2
t
23
2ns
SCLK Last Edge to SYNC Delay
2
t
24
3ns
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
2
t
28
See Table I
CNVST LOW to SYNC Asserted Delay t
29
1.25 µs
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figures 18 and 19 (Slave Serial Interface Modes)
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
318ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert Mode, see Table II.
Specifications subject to change without notice.
(–40C to +85C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. B
AD7676
–4–
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0011
DIVSCLK[0] 0101Unit
SYNC to SCLK First Edge Delay Minimum t
18
3171717ns
Internal SCLK Period Minimum t
19
25 50 100 200 ns
Internal SCLK Period Maximum t
19
40 70 140 280 ns
Internal SCLK HIGH Minimum t
20
12 22 50 100 ns
Internal SCLK LOW Minimum t
21
7214999ns
SDOUT Valid Setup Time Minimum t
22
4181818ns
SDOUT Valid Hold Time Minimum t
23
243089ns
SCLK Last Edge to SYNC Delay Minimum t
24
360140 300 ns
Busy High Width Maximum t
28
2 2.5 3.5 5.75 µs
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IN+
2
, IN–
2
, REF, REFGND
. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Inputs section.
3
Specification is for device in free air: 48-Lead LQFP: ␪
JA
= 91°C/W, ␪
JC
= 30°C/W.
4
Specification is for device in free air: 48-Lead LFCSP: ␪
JA
= 26°C/W.
TO OUTPUT
PIN
C
L
60pF
*
500A
I
OH
1.6mA
I
OL
1.4V
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
*
Figure 1. Load Circuit for Digital Interface Timing
0.8V
2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
Figure 2. Voltage Reference Levels for Timings
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7676 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Package
Model Temperature Range Package Description Option
AD7676AST –40°C to +85°CQuad Flatpack (LQFP) ST-48
AD7676ASTRL –40°C to +85°CQuad Flatpack (LQFP) ST-48
AD7676ACP –40°C to +85°CChip Scale (LFCSP) CP-48
AD7676ACPRL –40°C to +85°CChip Scale (LFCSP) CP-48
EVAL-AD7676CB
1
Evaluation Board
EVAL-CONTROL BRD2
2
Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for
evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
REV. B
AD7676
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin
2 AVDD P Input Analog Power Pins. Nominally 5 V.
3, 6, 7, NC No Connect
40–42,
44–48
4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary. When LOW, the MSB is inverted resulting in a twos complement output from its internal
shift register.
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected. When HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in
high impedance.
11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master
Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired,
the internal serial clock that clocks the data output. In the other serial modes, these pins are high
impedance outputs.
13 D[4] DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to
an external clock signal connected to the SCLK input.
14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Modes.
16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a Read Mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When
EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH,
the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output
on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface, Digital Power Ground
18 OVDD P Input/Output Interface, Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7676ASTZ

Mfr. #:
Buy AD7676ASTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 500kSPS CMOS 16-Bit w/ INL of 1 LSB Max
Lifecycle:
New from this manufacturer.
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