AD8033/AD8034
Rev. D | Page 16 of 24
THEORY OF OPERATION
The incorporation of JFET devices into the Analog Devices
high voltage XFCB process has enabled the ability to design the
AD8033/AD8034. The AD8033/AD8034 are voltage feedback
rail-to-rail output amplifiers with FET inputs and a bipolar-
enhanced common-mode input range. The use of JFET devices in
high speed amplifiers extends the application space into both the
low input bias current and low distortion, high bandwidth areas.
Using N-channel JFETs and a folded cascade input topology,
the common-mode input level operates from 0.2 V below the
negative rail to within 3.0 V of the positive rail. Cascading of
the input stage ensures low input bias current over the entire
common-mode range as well as CMRR and PSRR specifications
that are above 90 dB. Additionally, long-term settling issues that
normally occur with high supply voltages are minimized as a
result of the cascading.
OUTPUT STAGE DRIVE AND CAPACITIVE LOAD
DRIVE
The common emitter output stage adds rail-to-rail output
performance and is compensated to drive 35 pF (30% overshoot
at G = +1). Additional capacitance can be driven if a small snub
resistor is put in series with the capacitive load, effectively
decoupling the load from the output stage, as shown in Figure 12.
The output stage can source and sink 20 mA of current within
500 mV of the supply rails and 1 mA within 100 mV of the
supply rails.
INPUT OVERDRIVE
An additional feature of the AD8033/AD8034 is a bipolar input
pair that adds rail-to-rail common-mode input performance
specifically for applications that cannot tolerate phase inversion
problems.
Under normal common-mode operation, the bipolar input
pair is kept reversed, maintaining I
b
at less than 1 pA. When
the input common-mode operation comes within 3.0 V of the
positive supply rail, I1 turns off and I4 turns on, supplying tail
current to the bipolar pair Q25 and Q27. With this configuration,
the inputs can be driven beyond the positive supply rail without
any phase inversion (see Figure 53).
As a result of entering the bipolar mode of operation, an offset
and input bias current shift occurs (see Figure 32 and Figure 35).
After re-entering the JFET common-mode range, the amplifier
recovers in approximately 100 ns (refer to Figure 29 for input
overload behavior). Above and below the supply rails, ESD
protection diodes activate, resulting in an exponentially
increasing input bias current. If the inputs are driven well
beyond the rails, series input resistance should be included
to limit the input bias current to <10 mA.
INPUT IMPEDANCE
The input capacitance of the AD8033/AD8034 forms a pole
with the feedback network, resulting in peaking and ringing
in the overall response. The equivalent impedance of the
feedback network should be kept small enough to ensure that
the parasitic pole falls well beyond the −3 dB bandwidth of the
gain configuration being used. If larger impedance values are
desired, the amplifier can be compensated by placing a small
capacitor in parallel with the feedback resistor. Figure 13 shows
the improvement in frequency response by including a small
feedback capacitor with high feedback resistance values.
THERMAL CONSIDERATIONS
Because the AD8034 operates at up to ±12 V supplies in the
small 8-lead SOT-23 package (160°C/W), power dissipation can
easily exceed package limitations, resulting in permanent shifts
in device characteristics and even failure. Likewise, high supply
voltages can cause an increase in junction temperature even
with light loads, resulting in an input bias current and offset
drift penalty. The input bias current doubles for every 10°C
shown in Figure 31. Refer to the Maximum Power Dissipation
section for an estimation of die temperature based on load and
supply voltage.
AD8033/AD8034
Rev. D | Page 17 of 24
V
TH
+
V
S
R2
Q6
–IN
J1
D4
Q25
Q7
I2
Q27
R3
R14
Q9
–V
S
J2
+IN
R7
Q29
Q4
Q13
V
CC
Q11
I3
Q28
R8
Q1
Q14
V2
V4
+
+
V
OUT
D5
I1 I4
02924-053
Figure 53. Simplified AD8033/AD8034 Input Stage
AD8033/AD8034
Rev. D | Page 18 of 24
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
BYPASSING
Power supply pins are actually inputs, and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering a
majority of the noise. Decoupling schemes are designed to
minimize the bypassing impedance at all frequencies with a
parallel combination of capacitors. The chip capacitors, 0.01 µF
or 0.001 µF (X7R or NPO), are critical and should be placed as
close as possible to the amplifier package. Larger chip capacitors,
such as the 0.1 µF capacitor, can be shared among a few closely
spaced active components in the same signal path. The 10 µF
tantalum capacitor is less critical for high frequency bypassing, and
in most cases, only one per board is needed at the supply inputs.
GROUNDING
A ground plane layer is important in densely packed PCBs to
spread the current, thereby minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional
to the magnitude of the parasitic inductances and, thus, the
high frequency impedance of the path. High speed currents
in an inductive ground return create unwanted voltage noise.
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location.
Because load currents flow from the supplies as well, the ground
for the load impedance should be at the same physical location
as the bypass capacitor grounds. For the larger value capacitors
that are intended to be effective at lower frequencies, the current
return path distance is less critical.
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator material
can create leakage currents that are much larger than the input
bias currents of the AD8033/AD8034. Any voltage differential
between the inputs and nearby runs set up leakage currents
through the PCB insulator, for example, 1 V/100 G = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem). To significantly reduce
leakages, put a guard ring (shield) around the inputs and input
leads that is driven to the same voltage potential as the inputs.
This way there is no voltage potential between the inputs and
surrounding area to set up any leakage currents. For the guard
ring to be completely effective, it must be driven by a relatively
low impedance source and should completely surround the input
leads on all sides, above, and below using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials
such as Teflon® or ceramic may be necessary in some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance reduces the input impedance at
high frequencies, in turn it increases the gain of the amplifier
and can cause peaking of the overall frequency response or even
oscillations if severe enough. It is recommended that the external
passive components that are connected to the input pins be placed
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a distance of at
least 0.05 mm from the input pins on all layers of the board.

AD8034ARTZ-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Operational Amplifiers - Op Amps SOT23 Hi-Speed Dual FET Input Amplifier
Lifecycle:
New from this manufacturer.
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