AD8033/AD8034
Rev. D | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 26.4 V
Power Dissipation See Figure 5
If the rms signal levels are indeterminate, consider the worst case,
when V
OUT
= V
S
/4 for R
L
to midsupply
P
D
= (V
S
× I
S
) + (V
S
/4)
2
/R
L
In single-supply operation with R
L
referenced to V
S−
, worst case
is V
OUT
= V
S
/2.
Common-Mode Input Voltage 26.4 V
Differential Input Voltage 1.4 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
AMBIENT TEMPERATURE (°C)
–60 –20–40 10060 80
2.0
1.5
MAXIMUM POWER DISSIPATION (W)
1.0
0.5
0
SOIC-8
SOT-23-8
SC70-5
40020
02924-005
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8033/AD8034
packages is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic that encapsulates the die locally
reaches the junction temperature. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the AD8033/
AD8034. Exceeding a junction temperature of 175°C for an
extended period can result in changes in silicon devices, potentially
causing failure.
Figure 5. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
JA
. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps as discussed
in the Layout, Grounding, and Bypassing Considerations section.
Figure 5 shows the maximum power dissipation in the package
vs. the ambient temperature for the 8-lead SOIC (125°C/W),
5-lead SC70 (210°C/W), and 8-lead SOT-23 (160°C/W) packages
on a JEDEC standard 4-layer board. θ
JA
values are approximations.
The still-air thermal properties of the package and PCB (θ
JA
),
ambient temperature (T
A
), and the total power dissipated in the
package (P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8033/AD8034 will likely cause catastrophic failure.
T
J
= T
A
+ (P
D
× θ
JA
)
P
D
is the sum of the quiescent power dissipation and the power
dissipated in the package due to the load drive for all outputs.
The quiescent power is the voltage between the supply pins (V
S
)
times the quiescent current (I
S
). Assuming the load (R
L
) is
referenced to midsupply, the total drive power is V
S
/2 × I
OUT
,
some of which is dissipated in the package and some in the load
(V
OUT
× I
OUT
). The difference between the total drive power and
the load power is the drive power dissipated in the package
ESD CAUTION
P
D
= Quiescent Power + (Total Drive Power − Load Power)
P
D
= [V
S
× I
S
] + [(V
S
/2) × (V
OUT
/R
L
)] − [V
OUT
2
/R
L
]
RMS output voltages should be considered. If R
L
is referenced
to −V
S
, as in single-supply operation, the total drive power is
V
S
× I
OUT
.
