2200 MHz to 2700 MHz, Dual-Balanced
Mixer, LO Buffer, IF Amplifier, and RF
Balun
ADL5354
Rev. 0
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FEATURES
RF frequency range of 2200 MHz to 2700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.6 dB
SSB noise figure of 10.6 dB
Input IP3 of 26.1 dBm
Input P1dB of 10.6 dBm
Typical LO power of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
FUNCTIONAL BLOCK DIAGRAM
09118-001
ADL5354
VGS0
VGS1
VGS2
LOSW
PWDN
VPOS
COMM
LOI2
LOI1
MNIN
MNCT
COMM
DVIN
VPOS
COMM
VPOS
COMM
DVCT
V
P
O
S
D
V
G
M
C
O
M
M
D
V
O
P
D
V
O
N
D
V
L
E
V
P
O
S
D
V
L
G
N
C
M
N
O
N
C
O
M
M
M
N
G
M
V
P
O
S
M
N
O
P
M
N
L
E
V
P
O
S
M
N
L
G
N
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Figure 1.
GENERAL DESCRIPTION
The ADL5354 uses a highly linear, doubly balanced, passive mixer
core along with integrated RF and local oscillator (LO) balancing
circuitry to allow single-ended operation. The ADL5354 incor-
porates the RF baluns, allowing for optimal performance over a
2200 MHz to 2700 MHz RF input frequency range. The balanced
passive mixer arrangement provides good LO-to-RF leakage,
typically better than −37 dBm, and excellent intermodulation
performance. The balanced mixer core also provides extremely
high input linearity, allowing the device to be used in demanding
cellular applications where in-band blocking signals may other-
wise result in the degradation of dynamic performance. A high
linearity IF buffer amplifier follows the passive mixer core to yield
a typical power conversion gain of 8 dB and can be used with a
wide range of output impedances.
The ADL5354 provides two switched LO paths that can be used
in time division duplex (TDD) applications where it is desirable
to ping-pong between two local oscillators. LO current can be
externally set using a resistor to minimize dc current
commensurate with the desired level of performance. For low
voltage applications, the ADL5354 is capable of operation at
voltages as low as 3.3 V with substantially reduced current. For
low voltage operation, an additional logic pin is provided to
power down (~300 µA) the circuit when desired.
The ADL5354 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356
2200 to 2700 ADL5353 ADL5354
ADL5354
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
3.3 V Performance........................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
3.3 V Performance...................................................................... 14
Spur Tables ...................................................................................... 15
5 V Performance......................................................................... 15
3.3 V Performance...................................................................... 15
Circuit Description......................................................................... 16
RF Subsystem.............................................................................. 16
LO Subsystem ............................................................................. 16
Applications Information.............................................................. 18
Basic Connections...................................................................... 18
IF Port .......................................................................................... 18
Bias Resistor Selection ............................................................... 18
Mixer VGS Control DAC.......................................................... 18
Evaluation Board ............................................................................ 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
2/11—Revision 0: Initial Version
ADL5354
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
S
= 5 V, I
S
= 350 mA, T
A
= 25°C, f
RF
= 2535 MHz, f
LO
= 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 =
R5 = 1 k, Z
O
= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 20 dB
Input Impedance 50
RF Frequency Range 2200 2700 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage
1
Externally generated 3.3 5.0 5.5 V
LO INTERFACE
LO Power −6 0 +10 dBm
Return Loss 13 dB
Input Impedance 50
LO Frequency Range 1750 2670 MHz
POWER-DOWN (PWDN) INTERFACE
2
PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 230 ns
PWDN Input Bias Current Device enabled 0 µA
Device disabled 70 µA
1
Apply supply voltage from external circuit through choke inductors.
2
PWDN function is intended for use with V
S
≤ 3.6 V only.

ADL5354-EVALZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
ADL5354 Up-Down Converter and Mixer Evaluation Board
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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