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ADL5354-EVALZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ADL5354
Rev. 0 | Page 4 of 24
5 V PERFORMANCE
V
S
= 5 V, I
S
= 350 mA, T
A
= 25°C, f
RF
= 2535 MHz, f
LO
= 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
VGS0 = VGS1 = VGS2 = 0 V, and Z
O
= 50 Ω, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.6 dB
Voltage Conversion Gain Z
SOURCE
= 50 Ω, differential Z
LOAD
= 200 Ω differential 14.6 dB
SSB Noise Figure 10.6 dB
Input Third-Order Intercept (IIP3)
f
RF1
= 2534.5 MHz, f
RF2
= 2535.5 MHz, f
LO
= 2332 MHz,
each RF tone at −10 dBm
26.1 dBm
Input Second-Order Intercept (IIP2)
f
RF1
= 2535 MHz, f
RF2
= 2585 MHz, f
LO
= 2332 MHz,
each RF tone at −10 dBm
50 dBm
Input 1 dB Compression Point (IP1dB) 10.6 dBm
LO-to-IF Leakage Unfiltered IF output −20.7 dBm
LO-to-RF Leakage −37 dBm
RF-to-IF Isolation −34 dBc
IF/2 Spurious −10 dBm input power −73 dBc
IF/3 Spurious −10 dBm input power −71 dBc
IF Channel-to-Channel Isolation 52 dB
POWER SUPPLY
Positive Supply Voltage 4.75 5 5.25 V
Quiescent Current LO supply 170 mA
IF supply 180 mA
Total Quiescent Current V
S
= 5 V 350 mA
3.3 V PERFORMANCE
V
S
= 3.3 V, I
S
= 200 mA, T
A
= 25°C, f
RF
= 2535 MHz, f
LO
= 2332 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V,
and Z
O
= 50 , unless otherwise noted.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8 dB
Voltage Conversion Gain Z
SOURCE
= 50 Ω, differential Z
LOAD
= 200 Ω differential 14 dB
SSB Noise Figure 9.9 dB
Input Third-Order Intercept (IIP3)
f
RF1
= 2534.5 MHz, f
RF2
= 2535.5 MHz, f
LO
= 2332 MHz, each
RF tone at −10 dBm
17.5 dBm
Input Second-Order Intercept (IIP2)
f
RF1
= 2535 MHz, f
RF2
= 2585 MHz, f
LO
= 2332 MHz, each RF
tone at −10 dBm
49 dBm
Input 1 dB Compression Point (IP1dB) 7 dBm
POWER INTERFACE
Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 200 mA
Power-Down Current Device disabled 300 A
ADL5354
Rev. 0 | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage, V
S
5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
MNOP, MNON, DVOP, DVON Bias 6.0 V
VGS2,VGS1,VGS0, LOSW, PWDN 5.5 V
Internal Power Dissipation 2.2 W
Thermal Characteristic θ
JA
22°C/W
Maximum Junction Temperature 150°C
Temperature Range
Operating −40°C to +85°C
Storage −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADL5354
Rev. 0 | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
25
26
23
22
21
1
2
3
9
20
27
19
4
5
6
7
8
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
3
3
3
4
3
5
3
6
3
2
3
1
3
0
2
9
2
8
VGS0
VGS1
VGS2
LOSW
PWDN
VPOS
COMM
LOI2
LOI1
MNIN
MNCT
COMM
DVIN
VPOS
COMM
VPOS
COMM
DVCT
V
P
O
S
D
V
G
M
C
O
M
M
D
V
O
P
D
V
O
N
D
V
L
E
V
P
O
S
D
V
L
G
N
C
M
N
O
N
C
O
M
M
M
N
G
M
V
P
O
S
M
N
O
P
M
N
L
E
V
P
O
S
M
N
L
G
N
C
ADL5354
TOP VIEW
(Not to Scale)
NOTES
1
2
. NC = NO CONNECT.
. EXPOSED PAD MUST BE CONNECTED TO GROUND.
09118-002
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.
2 MNCT Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.
3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground).
4, 6, 10, 16, 21, 30, 36 VPOS Positive Supply Voltage.
8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.
11 DVGM Diversity Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
13, 14 DVOP, DVON
Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled up to
VCC using external inductors, see Figure 53 for details.
15 DVLE Diversity Channel IF Return. This pin must be grounded.
17 DVLG Diversity Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
18, 28 NC No Connect. Do not connect to this pin.
19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.
22 PWDN
Power Down. Connect this pin to ground for normal operation. Connect pin to 3 V for disable
mode when using VPOS ≤ 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26
VGS0, VGS1,
VGS2
Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to a low logic
level.
27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.
29 MNLG Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
31 MNLE Main Channel IF Return. This pin must be grounded.
32, 33 MNOP, MNON
Main Channel Differential Open-Collector Outputs. Pull up MNOP and MNON to VCC by using
external inductors, see Figure 53 for details.
35 MNGM Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
EPAD Exposed Paddle. Exposed pad must be connected to ground.
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ADL5354-EVALZ

Mfr. #:
Buy ADL5354-EVALZ
Manufacturer:
Analog Devices Inc.
Description:
ADL5354 Up-Down Converter and Mixer Evaluation Board
Lifecycle:
New from this manufacturer.
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