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TDA8034HN/C1,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 7 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.2 Voltage supervisor
The voltage supervisor monitors the voltage of the V
DDP
, V
DD
and V
DD(INTF)
supplies
providing both Power-On Reset (POR) and supply drop-out detection during a card
session. The supervisor threshold voltages for V
DDP
and V
DD
are set internally, and for
V
DD(INTF)
externally by pin PORADJ. As long as V
DD
is less than V
th
+ V
hys
, the IC remains
inactive irrespective of the command line levels. After V
DD
has reached a level higher than
V
th
+ V
hys
, the IC remains inactive for the duration of t
w
. The output of the supervisor is
sent to a digital controller in order to reset the TDA8034HN. This defined reset pulse of
approximately 8 ms, i.e. (t
w
= 1024
1
⁄
fosc(int)low
), is used internally to maintain the IC in
the Shutdown mode during the supply voltage power on; see Figure 4
. A deactivation
sequence is performed when either V
DD
, V
DDP
or V
DD(INTF)
falls below V
th
.
Remark: f
osc(int)low
is the low frequency (or inactive) mode of the defined f
osc(int)
parameter.
Fig 3. Voltage supervisor circuit
Fig 4. Voltage supervisor waveforms
001aal138
REFERENCE
VOLTAGE
V
DD
V
DD
PORADJ
VCC_SEL2
V
DDP
V
DD(INTF)
R1
R2
001aak993
t
w
t
w
power on supply dropout power off
V
th
+ V
hys
V
th
V
DD
ALARMN
(internal signal)
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 8 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.3 Clock circuits
The clock signal from pin CLK to the card is either supplied by an external clock signal
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and
XTAL2. The TDA8034HN automatically detects if an external clock is connected to
XTAL1, eliminating the need for a separate pin to select the clock source.
Automatic clock source detection is performed on each activation command (falling edge
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is
checked during a time window defined by the internal oscillator. If a clock is detected, the
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator
is started. When an external clock is used, it is mandatory that the clock is applied to pin
XTAL1 before the falling edge of the signal on pin CMDVCCN.
The clock frequency is selected using pins CLKDIV1 and CLKDIV1 to be either f
xtal
,
1
⁄
2
f
xtal
or
1
⁄
4
f
xtal
or
1
⁄
8
f
xtal
as shown in Table 4.
Remark: The levels on both pins must not be allowed to change simultaneously but
should be separated by a minimum of 10 ns.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of f
xtal
on pin CLK should be between 45 % and 55 %. If an external clock
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either f
xtal
,
1
⁄
2
f
xtal
,
1
⁄
4
f
xtal
or
1
⁄
8
f
xtal
,
the frequency dividers guarantee a duty cycle between 45 % and 55 %.
enclkin and clkxtal are internal signal names.
Fig 5. Basic layout for using an external clock
Table 4. Clock configuration
Pin CLKDIV1 level Pin CLKDIV2 level Pin CLK frequency
LOW LOW
1
⁄
8
f
xtal
LOW HIGH
1
⁄
4
f
xtal
HIGH HIGH
1
⁄
2
f
xtal
HIGH LOW f
xtal
001aak992
DIGITAL
MULTIPLEXER
CRYSTAL
XTAL1 XTAL2
clkxtalenclkin
TDA8034HN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3.4 — 29 June 2016 9 of 32
NXP Semiconductors
TDA8034HN
Low power smart card interface
8.4 Input and output circuits
When pins I/O and I/OUC are pulled HIGH using an 11 k resistor between pins I/O and
V
CC
and/or between pins I/OUC and V
DD(INTF)
, both lines enter the idle state. Pin I/O is
referenced to V
CC
and pin I/OUC to V
DD(INTF)
, thus allowing operation at V
CC
V
DD(INTF)
.
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay t
d
,
the logic 0 present on the master-side is sent to the slave-side. When the master-side
returns logic 1, the slave-side sends logic 1 during time delay (t
w(pu)
). After this sequence,
both master and slave sides return to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8034HN
capable of delivering more than 1 mA, up to an output voltage of 0.9V
CC
, at a load of
80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the
internal pull-up resistor value and load current. The current sent to and received from the
card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.
8.5 Shutdown mode
After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode,
ensuring only the minimum number of circuits are active while the TDA8034HN waits for
the microcontroller to start a session.
• all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
• pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 k pull-up
resistor connected to V
DD(INTF)
• the voltage generators are stopped
• the voltage supervisor is active
• the internal oscillator runs at its lowest frequency (f
osc(int)low
)
8.6 Deep shutdown mode
When the smart card reader is inactive, the TDA8034HN will enter Deep shutdown mode
if pin CMDVCCN is forced HIGH and pins VCC_SEL1 and VCC_SEL2 are LOW. In Deep
shutdown mode, all circuits are disabled and pin OFFN follows the status of pin PRESN.
Changing the status of either pin CMDVCCN, VCC_SEL1 or VCC_SEL2 exits Deep
shutdown mode; see Figure 6
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

TDA8034HN/C1,157

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Buy TDA8034HN/C1,157
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized SMART CARD INTERFACE
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New from this manufacturer.
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