Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
10
software reset is issued through command 3x of the Command
register (CR). The disable is done by setting the transmitter disable
bit also in the command register. If the transmitter is disabled, it
continues operating until the character currently being transmitted, if
any, is completely sent, including the stop bit. When reset the
transmitter stops immediately, drives the transmitter serial data out
put to a high level and discards any data in the TxFIFO.
Transmission of “break”s
Transmission of a break character is often needed as a
synchronizing condition in a data stream. The “break” is defined as a
start bit followed by all zero data bits by a zero parity bit (if parity is
enabled) and a zero in the stop bit position. The forgoing is the
minimum time to define a break. The transmitter can be forced to
send a break (continuous low condition) by issuing a start break
command via the CR. This command does not have any timing
associated with it. Once issued the TxD output will be driven low
(the spacing condition) and remain there until the host issues a
command to “stop break” via the CR or the transmitter is issued a
software or hardware reset. In normal operation the break is usually
much longer than one character time.
1x and 16x modes, Transmitter
The transmitter clocking has two modes: 16x and 1x. Data is
always sent at the 1x rate. However the logic of the transmitter may
be operated with a clock that is 16 times faster than the data rate or
at the same rate as the data i.e. 1x. All clocks selected internally
for the transmitter (and the receiver) will be 16x clocks. Only when
an external clock is selected may the transmitter logic and state
machine operate in the 1x mode. The 1x or 16x clocking makes
little difference in transmitter operation. (this is not true in the
receiver) In the 16X clock mode the transmitter will recognize a byte
in the TxFIFO within 1/16 to 2/16 bit time and thus begin
transmission of the start bit; in the 1x mode this delay may be up to
2 bit times.
Transmitter FIFO
The transmitter buffer memory is a 16 byte by 8 bit ripple FIFO. The
host writes characters to this buffer. This buffer accepts data only
when the transmitter is enabled. The transmitter state machine
reads them out in the order they were received and presents them to
the transmitter shift register for serialization. The transmitter adds
the required start, parity and stop bits as required the MR2 register
programming. The start bit (always one bit time in length) is sent
first followed by the least significant bit (LSB) to the most significant
bit (MSB) of the character, the parity bit (if used) and the required
stop bit(s).
Logic associated with the FIFO encodes the number of empty
positions available in a four bit value. This value is concatenated
with the channel number and type interrupt type identifier and
presented to the interrupt arbitration system. The encoding of the
”positions empty” value is always 1 less than the number of
available positions. Thus, an empty TxFIFO will bid with the value
or 15; when full it will not bid at all; one position empty bids with the
value 0. A full FIFO will not bid since a character written to it will be
lost
Normally a TxFIFO will present a bid to the arbitration system when
ever it has one or more empty positions. The MR0[5:4] allow the
user to modify this characteristic so that bidding will not start until
one of four levels (empty, 3/4 empty, 1/2 empty, not full) have been
reached. As will be shown later this feature may be used to make
slight improvements in the interrupt service efficiency. A similar
system exists in the receiver.
Receiver
The receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if
any),framing error or break condition, and presents the assembled
character and its status condition to the CPU via the RxFIFO. Three
status bits are FIFOed with each character received. The RxFIFO is
really 11 bits wide; eight data and 3 status. Unused FIFO bits for
character lengths less than 8 bits are set to zero. It is important to
note that receiver logic considers the entire message to be
contained within the start bit to the stop bit. It is not aware that a
message may contain many characters. The receiver returns to its
idle mode at the end of each stop bit! As described below it
immediately begins to search for another start bit which is normally,
of course, immediately forth coming.
1x and 16x mode, Receiver
The receiver operates in one of two modes; 1x and 16x. Of the two,
the 16x is more robust and the preferred mode. Although the 1x
mode may allow a faster data rate is does not provide for the
alignment of the receiver 1x data clock to that of the transmitter.
This strongly implies that the 1x clock of the remote transmitter is
available to the receiver; the two devices are physically close to
each other.
The 16x mode operates the receiver logic at a rate 16 times faster
than the 1x data rate. This allows for validation of the start bit,
validation of level changes at the receiver serial data input (RxD),
and a stop bit length as short as 9/16 bit time. Of most importance
in the 16x mode is the ability of the receiver logic to align the phase
of the receiver 1x data clock to that of the transmitter with an
accuracy of less than 1/16 bit time.
When the receiver is enabled ( via the CR register) it begins looking
for a high to low (mark to space) transition on the RxD input pin. If a
transition is detected, an internal counter running at 16 times the
data rate is reset to zero. If the RxD remains low and is still low
when the counter reaches a count of 7 the receiver will consider this
a valid start bit and begin assembling the character. If the RxD input
returns to a high state the receiver will reject the previous high to low
(mark to space) transition on the RxD input pin. This action is the
”validation” of the start bit and also establishes the phase of the
receiver 1x clock to that of the transmitter The counter operating at
16x the data rate is the generator for the 1x data rate clock. With
the phase of the receiver 1x clock aligned to the falling of the start
bit (and thus aligned to the transmitter clock) AND with a valid start
bit having been verified the receiver will continue receiving bits by
sampling the RxD input on the rising edge of the 1x clock that is
being generated by the above mentioned counter running 16 times
the data rate. Since the falling edge of the 1x clock was aligned to
falling edge of the start bit then the rising of the clock will be in the
”center” of the bit cell.
This action will continue until a full character has been assembled.
Parity , framing, and stop bit , and break status is then assembled
and the character and its status bits are loaded to the RxFIFO At
this point the receiver has finished its task for that character and will
immediately begin the search for another start bit.
Receiver Status Bits
There are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error,
overrun error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not
necessarily related to the a byte being received or a byte that is in
the RxFIFO. They are however developed by the receiver state
machine
