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SC28L198A1BE,528

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
43
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V)
V
CC
= 5.0 volts 10%; T
A
= –40 °C to +85°C; unless otherwise specified
SYMBOL FIG # PARAMETER LIMIT UNIT
MIN TYP MAX
Reset Timing
t
RES
1
RESET pulse width 10 Sclk
Bus Timing
t
AS
A0–A7 setup time before Sclk C3 rising edge 10 2 ns
t
AH
A0–A7 hold time after Sclk C3 rising edge 18 8 ns
t
CS
CEN setup time before Sclk C1 high (Sync) 5 3 ns
CEN setup time before Sclk C2 high (Async) 5 3 ns
t
CH
CEN hold time after Sclk C3 high (Sync) 14
1½Sclk
ns
CEN hold time after Sclk C4 high (Async) 25
1½Sclk
ns
t
STP
CEN high before next C2 to stop next cycle (Sync Mode)
2
18 ns
t
RWS
W–Rn setup time before Sclk C2 rising edge 5 ns
t
RWH
W–Rn hold time after Sclk C3 rising edge 14
1½Sclk
ns
t
DD
Read cycle Data valid after Sclk C3 rising edge 12 25 ns
t
DF
Read cycle data bus floating after CEN high (Sync) 10 16 ns
Read cycle data bus floating after C4 end high (Async) 10 15 ns
t
DS
Write cycle data setup time before Sclk C4 rising edge 25 14 ns
t
DH
Write cycle data hold time after Sclk C4 rising edge 15 8 ns
t
RWD
High time between CEN low (Async) 12
½ Sclk
ns
I/O Port Pin Timing
t
PS
I/O input setup time before Sclk C3 rising edge 18 4 ns
t
PH
I/O input hold time after Sclk C4 rising edge 12 1 ns
t
PD
I/O output valid from:
Write Sclk C4 rising edge (write to IOPIOR)
32 50 ns
Interrupt Timing
t
IR
IRQN from:
Internal interrupt source active bid
Reset to IRQN inactive
Write IMR (set or clear IMR bit)
3
22 26 43
75
45
Sclk
ns
ns
t
DD
IACKN cycle Data valid after Sclk C3 rising edge 12 25 ns
Tx/Rx Clock Timing
t
RX
RxC high or low time 15 8 ns
F
RX
4
RxC frequency (16 X)
(1 X)
0
0
16
1
Mhz
Mhz
t
TX
TxC high or low time 15 7 ns
F
TX
4
TxC frequency (16 X)
(1 X)
0
0
16
1
Mhz
Mhz
Transmitter Timing
t
TXD
TxD output delay from TxC low 32 60 ns
ttcs TxC output delay from TxD output data –15 4 15 ns
Receiver Timing
t
RXS
RxD data setup time to RxC high (data) 20 –4 ns
t
RXH
RxD data hold time from RxC high (data) 20 6 ns
ts
STRT
RxD data low time for receiving a valid Start Bit 17/32 bit
time
Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
44
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5 V) (Continued)
V
CC
= 5.0 volts 10 %; T
A
= –40 °C to +85 °C; unless otherwise specified
SYMBOL FIG# PARAMETER LIMITS UNIT
MIN TYP MAX
Sclk Timing
t
sclkl
Min low time at V
IL
(0.8V) 11 5 ns
t
sclkh
Min high time at V
IH
(2.0V) 11 5 ns
F
sclk
Sclk frequency 0.1 33 MHz
t/
RFsck
Sclk rise and fall time (0.8 to 2.0Volts) 3 ns
X1/X2 Communication Crystal Clock
Fx1
5
X1 clock frequency 1 3.6864 8.0 MHz
X1 L / H X1 Low / High time 32 135 ns
T/RFx1 X1 Rise and Fall time 10 ns
Counter/Timer Baud Rate Clock (External Clock Input)
FC/T
4
Clock frequency 0 8 MHz
TC/TLH C/T high and low time 15 11 ns
TC/TO Delay C/T clock external to output pin 48 60 ns
DTACK Timing
DAKdly DACK low from Sclk C4 rising edge 10 18 ns
DAKdlya DACK high from CEN high (Async) 11 20 ns
DAKdlys DACK high from C4 end rising edge (Sync) 11 20 ns
I/O Port External Clock
tgpirtx GPI to Rx/Tx clock out 32 50 ns
RxD setup to I/OP rising edge 1X mode 20 2 ns
I/OP falling edge to TxD out 1X mode 32 60 ns
Gout Timing
GPOtdd GPO valid after write to GPOR 100 ns
NOTES:
1. Timing is illustrated and referenced with respect to W–RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it
generates the several “C” timing as shown in the timing diagrams.
2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and
before the C2 time of the next cycle.
3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.
4. The minimum frequency values are not tested, but are guaranteed by design.
5. 1MHz specification is for crystal operation.
Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
45
DC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3 V)
V
CC
= 3.3 volts 10%; T
A
= –40 °C to +85°C; unless otherwise specified
LIMITS
SYMBOL PARAMETER TEST CONDITIONS MIN TYP
1
MAX UNIT
V
IL
V
IH
V
IH
Input low voltage
2
Input high voltage (except X1/CLK)
Input high voltage (X1/CLK)
V
SS
0.8 * V
CC
0.8 * V
CC
0.2 * V
CC
V
CC
V
CC
V
V
OL
3
V
OH
V
OL
3
Output low voltage
4
Output high voltage (except OD outputs)
Open Drain low voltage
I
OL
= 3.2mA
I
OH
= –400mA
I
OH
= –100mA
I
OL
= 10.0mA
0.8V
CC
0.9V
CC
0.15
<0.25
0.4
0.4
V
V
I
IL
I
IH
Input current low, I/O pins
Input current high, I/O pins
V
IN
= 0
V
IN
= V
CC
–5 <0.1
<0.1
+5
mA
I
L
Input leakage current V
IN
= 0 to V
CC
–5 <1 5
mA
I
ILCKX1
I
IHCKX1
X1/CLK input low current
X1/CLK input high current
V
IN
=V
SS
,X2=Open
V
IN
=V
CC
, X2=Open
–300
300
mA
I
OZH
I
OZL
Output off current high, 3–state data bus
Output off current low, 3–state data bus
V
IN
= Vcc
VI
N
= 0 –5
<.1
<.1
5
mA
mA
I
ODL
I
ODH
Open–drain output low current in off state
Open drain output high current in off state
V
IN
= 0
V
IN
= V
CC
–5 <.1
<.1
5
mA
I
CC
Power supply current
Operating mode 33 MHz
Static Power down (No clocks, Open drains off,
inputs at Vss or Vcc)
TTL Input levels
CMOS input levels
CMOS input levels
22
12
0.6
35
20
5
mA
mA
mA
NOTES:
1. Typical values are at +25 °C, typical supply voltage and typical processing parameters.
2. All voltage measurements are referenced to V
SS
. For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of 10 ns
maximum. For X1/CLK this swing is between 0.2V and 2.88V. all time measurements are referenced at input voltages of V
IL
and V
IH
as
appropriate.
3. Test conditions for itnerrupt and I/O outputs: CL = 50 pF. Test conditions for the rest of the outputs: C
L
= 60 pF.
4. Simultaneous switching more than 6 I/O port pins from 5 volts to 0 volts at full capacitive load may ground bounce on the output pins up to
0.95 volts.
5. All R
X
, T
X
, Brg Timer, I/O pins operating at 16 MHz. Sclk at 35 MHz and V
CC
at 5.6 volts. A worst–case environment.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

SC28L198A1BE,528

Mfr. #:
Buy SC28L198A1BE,528
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3V-5V 8CH UART INTEL/MOT INTRF
Lifecycle:
New from this manufacturer.
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