SC28L198A1BE,557 Datasheet SC28L198A1BE,528, SC28L198A1BE,557, SC28L198A1A,512 | P22-P24

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10

Table 8. CR – Command Register

CR is used to write commands to the Octal UART.

Bits 7:3 Bit 2 Bit 1 Bit 0

Channel Com-

mand codes

see “Command

Lock TxD and

RxFIFO en-

ables

Enable Tx Enable Rx

CR[2] – Lock TxD and RxFIFO enables

If set, the transmitter and receiver enable bits, CR[1:0] are not

significant. The enabled/disabled state of a receiver or transmitter

can be changed only if this bit is at zero during the time of the write

to the command register. WRITES TO THE UPPER BITS OF THE

CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the condition

of the receiver and transmitter. The bit provides a mechanism for

writing commands to a channel, via CR[7:3], without the necessity of

keeping track of or reading the current enable status of the receiver

and transmitter.

CR[1] – Enable Transmitter

A one written to this bit enables operation of the transmitter. The

TxRDY status bit will be asserted. When disabled by writing a zero

to this bit, the command terminates transmitter operation and resets

the TxRDY and TxEMT status bits. However, if a character is being

transmitted or if characters are loaded in the TxFIFO when the

transmitter is disabled, the transmission of the all character(s) is

completed before assuming the inactive state.

CR[0] – Enable Receiver

A one written to this bit enables operation of the receiver. If not in

the special wake up mode, this also forces the receiver into the

search for start bit state. If a zero is written, this command

terminates operation of the receiver immediately – a character being

received will be lost. The command has no effect on the receiver

status bits or any other control registers. If the special wake–up

mode is programmed, the receiver operates even if it is disabled

(see Wake–up Mode).

CR[7:3] – Miscellaneous Commands ( See Table below)

The encoded value of this field can be used to specify a single

command as follows:

00000 No command.

00001 Reserved

00010 Reset receiver. Resets the receiver as if a hardware reset

had been applied. The receiver is disabled and the FIFO

pointer is reset to the first location effectively discarding all

unread characters in the FIFO.

00011 Reset transmitter. Resets the transmitter as if a hardware

reset had been applied.

00100 Reset error status. Clears the received break, parity error,

framing error, and overrun error bits in the status register

(SR[7:4]). Used in character mode to clear overrun error

status (although RB, PE and FE bits will also be cleared),

and in block mode to clear all error status after a block of

data has been received.

00101 Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2]) to be

cleared to zero.

00110 Start break. Forces the TxD output low (spacing). If the

transmitter is empty, the start of the break condition will be

delayed up to two bit times. If the transmitter is active, the

break begins when transmission of the current character

is completed. If there are characters in the TxFIFO, the

start of break is delayed until those characters, or any

others loaded after it have been transmitted (TxEMT must

be true before break begins). The transmitter must be

enabled to start a break.

00111 Stop break. The TxD line will go high (marking) within two

bit times. TxD will remain high for one bit time before the

next character, if any, is transmitted.

01000 Assert RTSN. Causes the RTSN output to be asserted

(low).

01001 Negate RTSN. Causes the RTSN output to be negated

(high).

Note: The two commands above actually reset and

set, respectively, the I/O2 or I/O1 pin associated with

the I/OPIOR register.

01010 Reserved

01011 Reserved

01100 Reserved

01101 Block error status mode. Upon reset of the device or an

individual receiver, the block mode of receiver error status

accumulates as each character moves to the bottom of

the RxFIFO, the position from which it will be read. In this

mode of operation, the RxFIFO may contain a character

with non–zero error status for some time. The status will

not reflect the error character’s presence until it is ready to

be popped from the RxFIFO. Command 01101 allows the

error status to be updated as each character is pushed

into the RxFIFO. This allows the earliest detection of a

problem character, but complicates the determination of

exactly which character is causing the error. This mode of

block error accumulation may be exited only by resetting

the chip or the individual receiver.

01111 Reserved.

10000 Transmit an Xon Character

10001 Transmit an Xoff Character

10010 Reserved for channels b–h, for channel a: enables a

Gang Write of Xon Character Registers. After this

command is issued, a write to the channel A Xon

Character Register will result in a write to all channel’s

Xon character registers. This command provides a

mechanism to initialize all the Xon Character registers

with one write. A write to channel A Xon Character

write mode.

10011 Reserved for channels b–h, for channel a: enables Gang

Write of Xoff Character Registers. After this command is

issued, a write to the channel A Xoff Character Register

will result in a write to all channel’s Xoff character

registers. This command provides a mechanism to

initialize all the Xoff Character registers with one write. A

write to channel A Xoff Character Register returns the

Octal UART to the individual Xoff write mode.

Note: Gang writing of Xon/Xoff Character Commands: Issuing

command causes the next write to Xon/Xoff Character Register

A to effect a simultaneous write into the other 3 Xon/Xoff

character registers. After the Xon/Xoff Character Register A is

written, the 28L198 returns to individual write mode for the

Xon/Xoff Character Registers. Other intervening reads and

writes are ignored. The device resets to individual write mode.

10100 Reserved for channels b-h, for channel a: executes a Gang

Load of Xon Character Registers. Executing this

command causes a write of the value x’11 to all channel’s

Xon character registers. This command provides a

mechanism to initialize all the Xon Character registers to a

default value with one write. Execution of this command

is immediate and does not effect the timing of subsequent

host I/O operations.

10101 Reserved for channels b-h, for channel a: executes a

Gang Load of Xoff Character Registers. Executing this

command causes a write of the value x’13 to all channel’s

Xoff character registers. This command provides a

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10

mechanism to initialize all the Xoff Character registers to a

default value with one write. Execution of this command

is immediate and does not effect the timing of subsequent

host I/O operations.

10110 Xoff resume command (CRXoffre; not active in

“Auto-Transmit Mode”). A command to cancel a previous

Host Xoff command. Upon receipt, the channel’s

transmitter will transfer a character, if any, from the

TxFIFO and begin transmission.

10111 Host Xoff command (CRXoff). This command allows tight

host CPU control of the flow control of the channel

transmitter. When interrupted for receipt of an Xoff

character by the receiver, the host may stop transmission

of further characters by the channel transmitter by issuing

the Host Xoff command. Any character that has been

transferred to the TxD shift register will complete its

transmission, including the stop bit.

11000 Cancel Host transmit flow control command. Issuing this

command will cancel a previous transmit command if the

flow control character is not yet loaded into the TxD Shift

or if its transmission has already begun, then this

command has no effect.

11001–11011

Reserved

11011 Reset Address Recognition Status. This command clears the

interrupt status that was set when an address character

was recognized by a disabled receiver operating in the

special mode.

11100–11101

Reserved

11110 Resets all UART channel registers. This command

provides a means to zero all the UART channels that are

not reset to x’00 by a reset command or a hardware reset.

11111 Reserved for channels b-h, for channel a: executes a chip

wide reset. Executing this command in channel a is

equivalent to a hardware reset with the RESETN pin.

Executing in channel b-h, has no effect.

Table 9. Command Register Code

Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.

Channel Command

Code

Channel

Command

Channel Command

Code

Channel

Command

CR[7:3] Description CR[7:3] Description

00000 NOP 10000 Transmit Xon

00001 Reserved 10001 Transmit Xoff

00010 Reset Receiver 10010 Gang Write Xon Character Registers *

00011 Reset Transmitter 10011 Gang Write Xoff Character Registers *

00100 Reset Error Status 10100 Gang Load Xon Character Registers DC1 *

00101 Reset Break Change Interrupt 10101 Gang Load Xoff Character Registers DC3 *

00110 Begin Transmit Break 10110 Xoff Resume Command

00111 End Transmit Break 10111 Host Xoff Command

01000 Assert RTSN (I/O2 or I/O1) 11000 Cancel Transmit X Char command

01001 Negate RTSN (I/O2 or I/O1) 11001 Reserved

01010 Set time–out mode on 11010 Reserved

01011 Reserved 11011 Reset Address Recognition Status

01100 Set time–out mode off 11100 Reserved

01101 Block Error Status configure 11101 Reserved

01110 Reserved 11110 Reset All UART channel registers

01111 Reserved 11111 Reset Device *

Table 10. SR – Channel Status Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Received

Break

Framing Error Parity

Error

Overrun Error TxEMT TxRDY RxFULL RxRDY

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

SR[7] – Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received; further entries to the

FIFO are inhibited until the RxD line returns to the marking state for

at least one half bit time (two successive edges of the internal or

external 1x clock). When this bit is set, the change in break bit in

the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break

condition, as defined above, is detected. The break detect circuitry

is capable of detecting breaks that originate in the middle of a

received character. However, if a break begins in the middle of a

character, it must last until the end of the next character in order for

it to be detected.

SR[6] – Framing Error (FE)

This bit, when set, indicates that a stop bit was not detected when

the corresponding data character in the FIFO was received. The

stop bit check is made in the middle of the first stop bit position.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10

SR[5] – Parity Error (PE)

This bit is set when the ’with parity’ or ’force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity. In the special ’wake up mode’, the

parity error bit stores the received A/D bit.

SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the RxFIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost. This bit is

cleared by a reset error status command.

SR[3] – Transmitter Empty (TxEMT)

This bit is set when the transmitter underruns, i.e., both the TxFIFO

and the transmit shift register are empty.

It is set after transmission of the last stop bit of a character, if no

character is in the TxFIFO awaiting transmission. It is reset when

the TxFIFO is loaded by the CPU, or when the transmitter is

disabled.

SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO is ready to be loaded

with a character. This bit is cleared when the TxFIFO is loaded by

the CPU and is set when the last character is transferred to the

transmit shift register. TxRDY is reset when the transmitter is

disabled and is set when the transmitter is first enabled, e.g.,

characters loaded in the TxFIFO while the transmitter is disabled will

not be transmitted.

SR[1] – RxFIFO Full (RxFULL)

This bit is set when a character is transferred from the receive shift

become full, i.e., all sixteen RxFIFO positions are occupied. It is

reset when the CPU reads the RxFIFO and that read leaves one

empty byte position. If a character is waiting in the receive shift

second read of the RxFIFO since the waiting character is

immediately loaded to the RxFIFO.

SR[0] – Receiver Ready (RxRDY)

This bit indicates that a character has been received and is waiting

in the RxFIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the RxFIFO and reset

when the CPU reads the RxFIFO, and no more characters are in the

RxFIFO.

Table 11. ISR – Interrupt Status Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

I/O Port

change of

state

Receiver

Watch-dog

Time–out

Address recogni-

tion event

Xon/off

event

Always 0 Change of

Break State

RxRDY

Receiver has entered

arbitration process

TxRDY

Transmitter has entered

arbitration process

This register provides the status of all potential interrupt sources for

a UART channel. When generating an interrupt arbitration value,

the contents of this register are masked by the interrupt mask

the IMR is also a ’1’, interrupt arbitration for this source will begin. If

the corresponding bit in the IMR is a zero, the state of the bit in the

ISR can have no affect on the IRQN output. Note that the IMR may

or may not mask the reading of the ISR as determined by MR1[6].

If MR1[6] is cleared, the reset and power on default, the ISR is read

without modification. If MR1[6] is set, the a read of the ISR gives a

value of the ISR ANDed with the IMR.

ISR[7] – Input Change of State

This bit is set when a change of state occurs at the I/O1 or I/O0

input pins. It is reset when the CPU reads the Input Port Register,

IPR.

ISR[6] Watch-dog Time–out

This bit is set when the receiver’s watch-dog timer has counted

more than 64 bit times since the last RxFIFO event. RxFIFO events

are a read of the RxFIFO or GRxFIFO, or the push of a received

character into the FIFO. The interrupt will be cleared automatically

upon the push of the next character received or when the RxFIFO or

GRxFIFO is read. The receiver watch-dog timer is included to allow

detection of the very last characters of a received message that may

be waiting in the RxFIFO, but are too few in number to successfully

initiate an interrupt. Refer to the watch-dog timer description for

details of how the interrupt system works after a watch-dog

time–out.

ISR[5] – Address Recognition Status Change

This bit is set when a change in receiver state has occurred due to

an Address character being received from an external source and

comparing to the reference address in ARCR. The bit and interrupt

is negated by a write to the CR with command x11011, Reset

Address Recognition Status.

ISR[4] – Xon/Xoff Status Change

This bit is set when an Xon/Xoff character being received from an

external source. The bit is negated by a read of the channel Xon

Interrupt Status Register, XISR.

ISR[3] – Reserved Always reads a 0

ISR[2] – Change in Channel Break Status

This bit, when set, indicates that the receiver has detected the

beginning or the end of a received break. It is reset when the CPU

issues a reset break change interrupt command via the CR.

ISR[1] – Receiver Ready

The general function of this bit is to indicate that the RxFIFO has

data available. The particular meaning of this bit is programmed by

MR2[3:2]. If programmed as receiver ready(MR2[3:2] = 00), it

indicates that at least one character has been received and is

waiting in the RxFIFO to be read by the host CPU. It is set when the

character is transferred from the receive shift register to the RxFIFO

and reset when the CPU reads the last character from the RxFIFO.

If MR2[3:2] is programmed as FIFO full, ISR[1] is set when a

character is transferred from the receive holding register to the

RxFIFO and the transfer causes the RxFIFO to become full, i.e. all

sixteen FIFO positions are occupied. It is reset when ever RxFIFO

is not full. If there is a character waiting in the receive shift register

because the FIFO is full, the bit is set again when the waiting

character is transferred into the FIFO.

The other two conditions of these bits, 3/4 and half full operate in a

similar manner. The ISR[1] bit is set when the RxFIFO fill level

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57

SC28L198A1BE,557

Mfr. #:

Buy SC28L198A1BE,557

Manufacturer:

NXP Semiconductors

Description:

UART Interface IC 3V-5V 8CH UART

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

SC28L198A1BE,557

SC28L198A1BE,557

Products related to this Datasheet