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SC28L198A1BE,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
46
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3 V)
V
CC
= 3.3 volts 10%; T
A
= –40 °C to +85°C; unless otherwise specified
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
MIN TYP MAX
UNIT
Reset Timing
t
RES
1
RESET pulse width 10 Sclk
Bus Timing
t
AS
A0-A7 setup time before Sclk C3 rising edge 22 3 ns
t
AH
A0-A7 hold time after Sclk C3 rising edge 30 12 ns
t
CS
CEN setup time before Sclk C1 high (ASYNC) 8 3 ns
t
CS
CEN setup time before Sclk C2 high (SYNC) 8 3 ns
t
CH
CEN hold time after Sclk C3 high (SYNC) 25
1½ Sclk
ns
t
CH
CEN hold time after Sclk C4 high (ASYNC) 50
1½ Sclk
ns
t
STP
Cen high befoe next C2 to stop next cycle (Sync Mode)
2
30 ns
t
RWS
W-Rn setup time before Sclk C2 rising edge 7 ns
t
RWH
W-Rn hold time after Sclk C3 rising edge 25
1½ Sclk
ns
t
DD
Read cycle Data valid after Sclk C3 falling edge 20 40 ns
t
DF
Read cycle data bus floating after CEN high (ASYNC) 17 30 ns
t
DF
Read cycle data bus floating after C4 end (SYNC) 11 20 ns
t
DS
Write cycle data setup time before Sclk C4 rising edge 25 14 ns
t
DH
Write cycle data hold time after Sclk C4 rising edge 25 14 ns
t
RWD
High time between CEN low (ASYNC) 15
½ Sclk
ns
I/O Port Pin Timing
t
PS
I/O input setup time before Sclk C3 falling edge (Read IPR) 18 4 ns
t
PH
I/O input hold time after Sclk C4 rising edge (Read IPR) 12 4 ns
t
PD
I/O output valid from:
Write Sclk C4 rising edge (write to I/OPIOR)
50 80 ns
Interrupt Timing
t
IR
IRQN from:
Internal interrupt source active bid
Software reset to IRQN inactive
Write IMR (set or clear IMR bit))
3
to IRQN inactive
22 26
60
40
43
90
60
Sclk
ns
ns
t
DD
Interrupt vector valid after C3 rising edge 20 30 ns
Tx / Rx Clock Timing, External
t
RX
RxC high or low time 25 8 ns
f
RX
4
RxC frequency (16 X)
(1 X)
0
0
8
1
MHz
t
TX
TxC high or low time 20 7 ns
f
TX
4
TxC frequency (16 X)
(1 X)
0
0
8.0
1
MHz
MHz
Transmitter Timing
t
TXD
TxD output delay from TxC low 50 90 ns
t
TCS
TxC output delay from TxD output data -15 4 15 ns
Receiver Timing
t
RXS
RxD data setup time to RxC high (data) 25 14 ns
t
RXH
RxD data hold time from RxC high (data) 25 14 ns
ts
STRT
RxD data low time to for receiving a valid Start Bit
17
32
bit time
Sclk Timing
t
SCLKL
Min low time at Vil (0.8V) 15 10 ns
t
SCLKH
Min high time at Vih (2.0V) 15 10 ns
Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
47
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3 V) (Continued)
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
MIN TYP MAX
UNIT
Fsclk Sclk frequency 0.1 20 MHz
T/RFsclk Sclk rise/fall time (0.8 to 2.0Volts) 5 ns
X1 / X2 Communication Crystal Clock
Fx1
5
X1 clock frequency 1 3.6864 4 MHz
X1 L / H X1 Low / High time 80 52 ns
T/RFx1 X1 Rise / Fall time 10 ns
Counter/Timer Baud Rate Clock (External Clock Input)
FC/T
4
Clock frequency 0 8 MHz
TC/TLH C/T high and low time 20 15 ns
TC/TO Delay C/T clock external to output pin 48 110 ns
DACKN Timing
DAK
DLY
DACK low from Sclk C4 rising edge 18 30 ns
DAK
DLYA
DACK high from CEN high (ASYNC) 18 30 ns
DAK
DLY
DACK high from C4 end rising edge (SYNC) 20 30 ns
I/O PORT External Clock
T
GPIRTX
GPI to Rx/Tx clock out 50 80 ns
RxD setup to I/OP rising edge 1X mode 20 2 ns
I/OP falling edge to TxD out 1X mode 32 70 ns
G
OUT
Timing
GPO
TDD
GPO valid after write to GPOR 100 ns
NOTES:
1. Timing is illustrated and referenced with respect to W–RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it
generates the several “C” timing as shown in the timing diagrams.
2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and
before the C2 time of the next cycle.
3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.
4. The minimum frequency values are not tested, but are guaranteed by design.
5. 1MHz specification is for crystal operation.
Philips Semiconductors Product data sheet
SC28L198Octal UART for 3.3 V and 5 V supply voltage
2006 Aug 10
48
SCLK
CEN
W_RN
ADDRESS
DATA
DACKN
INVALID VALID
C1 C2 C3 C4
t
CS
INVALID
INVALID VALID INVALID
t
RWS
t
AS
t
AH
t
DS
DAK
DLY
t
DH
C4
DAK
DLY
CEN HIGH
t
CH
t
RWD
t
RWH
SD00194
Figure 2. Basic Write Cycle, ASYNC
SCLK
CEN
W_RN
ADDRESS
DATA
DACKN
INVALID VALID
C1 C2 C3 C4
t
CS
INVALID
INVALID VALID INVALID
t
RWS
t
AS
t
AH
t
DS
DAK
DLY
t
DH
C4
DAK
DLY
C4 END
t
CH
t
STP
t
RWH
SD00195
C1 C2
Figure 3. Basic Write Cycle, SYNC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

SC28L198A1BE,557

Mfr. #:
Buy SC28L198A1BE,557
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 3V-5V 8CH UART
Lifecycle:
New from this manufacturer.
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