Document Number: 001-53145 Rev. *G Page 10 of 16
AC Electrical Characteristics
[7]
Parameter Description Condition Min Typ Max Unit
F
OUT
Output frequency
[8]
50 – 690 MHz
FSC Frequency stability, commercial
devices
[9]
V
DD
= min to max, T
A
= 0 °C to 70 °C – – ±35 ppm
FSI Frequency stability, industrial
devices
[9]
V
DD
= min to max, T
A
= –40 °C to 85 °C – – ±55 ppm
AG Aging, 10 years – – ±15 ppm
T
DC
Output duty cycle F 450 MHz, measured at zero crossing 45 50 55 %
F > 450 MHz, measured at zero crossing 40 50 60 %
T
R
, T
F
Output rise and fall time 20% and 80% of full output swing – 0.35 1.0 ns
T
LOCK
Startup time Time for CLK to reach valid frequency
measured from the time when
V
DD
= V
DD
(min.)
––5ms
T
LSER
Relock time Time for CLK to reach valid frequency from
serial bus change to select bits in register
40h, measured from I
2
C STOP
––1ms
T
Jitter()
RMS phase jitter (random) F
OUT
= 106.25 MHz (12 kHz to 20 MHz) – 1 – ps
Pre-defined factory configurations
[10]
See Note 10 ps
I
2
C Bus Timing Specifications
[7]
Parameter Description Min Max Unit
f
SCLK
SCLK frequency – 100 kHz
t
HD:STA
Start mode time from SDA LOW to SCLK LOW 4 – s
t
LOW
SCLK LOW period 4.7 – s
t
HIGH
SCLK HIGH period 4–s
t
SU:DAT
Input data setup (SDA transition to SCLK rising edge) 1000 – ns
t
HD:DAT
Input data hold (SCLK falling edge to SDA transition) 0 – ns
t
HD:DO
Output data hold (SCLK falling edge to SDA transition) 200 – ns
t
SR
Rise time of SCLK and SDA – 300 ns
t
SF
Fall time of SCLK and SDA – 300 ns
t
SU:STO
Stop mode time from SCLK HIGH to SDA HIGH 4 – s
t
BUF
Stop mode to start mode 4.7 – s
Notes
7. Not 100% tested, guaranteed by design and characterization.
8. This parameter is specified in CyClockWizard software.
9. Frequency stability is the maximum variation in frequency from F
0
. It includes initial accuracy, plus variation from temperature and supply voltage.
10. Typical phase noise specs for factory programmed devices are listed in the “Standard and Application-Specific Factory Configurations” on page 4.
