CY2XF23FLXIT Datasheet CY2XF23LXI625T, CY2XF23FLXIT, CY2XF23FLXCT | P4-P6

CY2XF23

Document Number: 001-53145 Rev. *G Page 4 of 16

Functional Description

The CY2XF23 is a PLL-based high-performance clock

generator. It uses an internal crystal oscillator as a reference,

and outputs one differential LVDS clock. It has an I

C bus serial

interface

[1]

, which is used to change the output frequency.

The CY2XF23 comes configured for four different frequencies.

At power-on, the four configurations are transparently loaded

into an internal volatile memory which, in turn, controls the PLL.

The user can switch between the four frequencies through the

C bus. The user can also configure the CY2XF23 with new

output frequencies by shifting new data into the internal memory.

Frequency margining is a common application for this feature.

One frequency is used for the standard operating mode of the

device, while additional frequencies are available for margin

testing, either during product development or in-system

manufacturing test.

Note that all configuration changes made using I

C are

temporary and are lost when power is removed from the device.

At power-on, the device returns to its original state.

The configuration for a particular frequency is stored in a 6-byte

block of memory, known as a word. The CY2XF23 has four such

words, labeled ‘Frequency Word 0’ through ‘Frequency Word 3’.

An additional register byte contains a 2-bit field, which selects

one of the four frequency words. By writing to this select byte,

the user can switch back and forth between the four programmed

frequencies. The select byte can be configured to select any of

the four frequency words at power-on.

When changing the output frequency, the frequency transition is

not guaranteed to be smooth. There can be frequency

excursions beyond the start frequency and the new frequency.

Glitches and runt pulses are possible, and time must be allowed

for the PLL to re-lock.

If more than four frequencies are needed, the I

C bus can be

used to change any of the four frequency words. When writing

frequency words through I

C, the users should not change the

currently selected word. Instead, write one of the three

unselected words before changing the select byte to select that

new word.

Figure 2 shows how the frequency words are arranged and

selected.

Figure 2. Frequency Words

Configuration Software

Cypress provides CyClockWizard™ software that enables the

users to create data values for shifting into the frequency words.

This software is required because the algorithm is too

complicated to be described here.

The user specifies the output frequency. The software then

calculates the bit stream for up to four frequency words, as

outlined by the register addresses for each word seen in

Figure 2.

Standard and Application-Specific Factory Configurations

Part Number Output Frequency Frequency Word

RMS Phase Jitter (Random)

Offset Range Jitter (Typical)

CY2XF23LXC001T 100.00 MHz (default)

95.00 MHz

103.000007 MHz

104.999993 MHz

637 kHz to 10 MHz

0.52 ps

–

Note

1. The serial interface is I

C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped to V

setup time, and output hold time.

10h – 15h Frequency Word 0

PLL

Frequency Word 1

Frequency Word 2

Frequency Word 3

16h – 1Bh

1Ch – 21h

22h – 27h

Select Byte40h

Bits [1:0]

Address

Sel

Control

CY2XF23

Document Number: 001-53145 Rev. *G Page 5 of 16

Programming Description

The CY2XF23 is a programmable device. Before being used in

an application, it must be programmed with the output

frequencies and other variables described in Programming

Variables on page 5. Two different device types are available,

each with its own programming flow. They are described in the

following sections.

Field-Programmable CY2XF23F

Field-programmable devices are shipped unprogrammed and

must be programmed before being installed on a printed circuit

board (PCB). Customers use CyClockWizard™ software to

specify the device configuration and generate a joint electron

devices engineering council (JEDEC - extension .jed)

programming file. Programming of samples and prototype

quantities is available using the CyClockWizard software along

with a CY3675-CLKMAKER1 CyClockMaker Clock Programmer

Kit with a CY3675-LCC6A socket adapter. Cypress’s value

added distribution partners also provide programming services.

Field programmable devices are designated with an ‘F’ in the

part number. They are intended for quick prototyping and

inventory reduction. The software and programmer kit hardware

can be downloaded from www.cypress.com by clicking the

hyperlinks above.

Factory-Configured CY2XF23

For ready-to-use devices, the CY2XF23 is available with no field

programming required. Pre-configured devices (see “Standard

and Application-Specific Factory Configurations” on page 4) are

available for samples or orders, or a request for a custom

configuration can be made. All requests are submitted to the

local Cypress Field Application Engineer (FAE) or sales

representative. After the request is processed, the user receives

a new part number, samples, and datasheet with the

programmed values. This part number is used for additional

sample requests and production orders. The CY2XF23 is

one-time programmable (OTP).

Programming Variables

Output Frequencies

The CY2XF23 is programmed with up to four independent output

frequencies, which are then selected using the I

C interface. The

device can synthesize frequencies to a resolution of 1 part per

million (ppm), but the actual accuracy of the output frequency is

limited by the accuracy of the integrated reference crystal.

The CY2XF23 has an output frequency range of 50 MHz to

690 MHz, but the range is not continuous. The CY2XF23 cannot

generate frequencies in the ranges of 521 MHz to 529 MHz and

596 MHz to 617 MHz.

Industrial versus Commercial Device Performance

Industrial and commercial devices have different internal

crystals. They have a potentially significant impact on

performance levels for applications requiring the lowest possible

phase noise. CyClockWIzard software allows the user to select

between and view the expected performance of both options.

Memory Map

Five fields can be written via the I

C bus. Four frequency words

define the output frequency. As shown in Table 2, each of these

words is a 6-byte field. When writing to a frequency word, all six

bytes should be written. They may be written either as individual

byte writes, or as a block write. The currently selected frequency

word should not be written to. All four words are symmetrical,

meaning that a 6-byte value that is valid for one word is also valid

for any of the other words, and produces the same frequency.

The fifth field is the select byte, located at byte address 40h. The

value written into the two least significant bits determines the

active frequency word. The other bits of the byte are reserved

and must be written with the values indicated in the table. Users

should never write to any address other than the 25 bytes

described here.

Serial Interface Protocol and Timing

The CY2XF23 uses pins SDA and SCLK for an I

C bus that

operates up to 100 kbits/sec in read or write mode. The

CY2XF23 is always a slave on this bus, meaning that it never

initiates a bus transaction. The basic write protocol is as follows:

Start Bit; 7-bit Device Address (DA); R/W

Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; and so on, until STOP Bit. The basic serial format

is illustrated in Figure 4 on page 7.

Table 1. Device Programming Variables

Variable

Output frequency 0

Output frequency 1

Output frequency 2

Output frequency 3

Temperature range (commercial or industrial)

Table 2. Frequency Words

Frequency

Word

Byte Addresses

(hex)

Word Select

(Select Byte 40h)

0 10h to 15h 00

1 16h to 1Bh 01

2 1Ch to 21h 10

3 22h to 27h 11

Table 3. Register 40h: Select Byte

Bits

Default Value

(binary)

Name Description

7:2 000000 Reserved Reserved. Always write

this value.

1:0 User-defined Word select Selects the Frequency

Word to determine the

output frequency. 00

selects Word 0; 01

selects Word 1; 10

selects Word 2; 11

selects Word 3.

CY2XF23

Document Number: 001-53145 Rev. *G Page 6 of 16

Device Address

The device I

C address is a 7-bit value. The default I

C address,

which appears in CyClockWizard is 69H, which can be changed

to any other value while generating configuration using

CyClockWizard. Note that the Field Programmable

(unprogrammed

[2]

) devices has default address as 59H.

Data Valid

Data is valid when the clock is HIGH, and may only be

transitioned when the clock is LOW as illustrated in Figure 5 on

page 7.

Data Frame

Every new data frame is indicated by a start and stop sequence,

as illustrated in Figure 6 on page 8.

START Sequence - Start frame is indicated by SDA going LOW

when SCLK is HIGH. Every time a start signal is given, the next

8-bit data must be the device address (seven bits) and a R/W

bit,

followed by register address (eight bits) and register data (eight

bits).

STOP Sequence - Stop frame is indicated by SDA going HIGH

when SCLK is HIGH. A stop frame frees the bus for writing to

another part on the same bus or writing to another random

Acknowledge Pulse

During write mode, the CY2XF23 responds with an

Acknowledge (ACK) pulse after every eight bits. This is

accomplished by pulling the SDA line LOW during the N*9

clock

cycle as illustrated in Figure 7 on page 8. (N = the number of

bytes transmitted). After the data packet is sent during read

mode, the master generates the acknowledge.

Write Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is followed

by an acknowledge bit from the slave (SDA = 0/LOW). The next

eight bits must contain the data word intended for storage. After

the data word is received, the slave responds with another

acknowledge bit (SDA = 0/LOW), and the master must end the

write sequence with a STOP condition.

Writing Multiple Bytes

To write more than one byte at a time, the master does not end

the write sequence with a stop condition. Instead, the master can

send multiple contiguous bytes of data to be stored. After each

byte, the slave responds with an acknowledge bit, just like after

the first byte, and accepts data until the acknowledge bit is

responded to by the STOP condition. When receiving multiple

bytes, the CY2XF23 internally increments the register address.

Read Operations

Read operations are initiated the same way as write operations

except that the R/W bit of the slave address is set to ‘1’ (HIGH).

There are three basic read operations: current address read,

random read, and sequential read.

Current Address Read

The CY2XF23 has an onboard address counter that retains 1

more than the address of the last word access. If the last word

written or read was word ‘n’, then a current address read

operation would return the value stored in location ‘n+1’. When

the CY2XF23 receives the slave address with the R/W bit set to

a ‘1’, the CY2XF23 issues an acknowledge and transmits the

8-bit word. The master device does not acknowledge the

transfer, but does generate a STOP condition, which causes the

CY2XF23 to stop transmission.

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first the

word address must be set. This is accomplished by sending the

address to the CY2XF23 as part of a write operation. After the

word address is sent, the master generates a START condition

following the acknowledge. This terminates the write operation

before any data is stored in the address, but not before the

internal address pointer is set. Next the master reissues the

control byte with the R/W byte set to ‘1’. The CY2XF23 then

issues an acknowledge and transmits the 8-bit word. The master

device does not acknowledge the transfer, but does generate a

STOP condition which causes the CY2XF23 to stop

transmission.

Sequential Read

Sequential read operations follow the same process as random

reads except that the master issues an acknowledge instead of

a STOP condition after transmission of the first 8-bit data word.

This action results in an incrementing of the internal address

pointer, and subsequently output of the next 8-bit data word. By

continuing to issue acknowledges instead of STOP conditions,

the master may serially read the entire contents of the slave

device memory. When the internal address pointer points to the

FFh register, after the next increment, the pointer will point to the

00h register.

Note

2. Field programmable devices are shipped unprogrammed and must be programmed before being installed on a PCB. An unprogrammed device will output the crystal

frequency of the integrated crystal (25 MHz for commercial and 38.8 MHz for industrial).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

CY2XF23FLXIT

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Manufacturer:

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Phase Locked Loops - PLL HI PERFORMANCE LVDS OSCILLATOR

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