CY2XF23
Document Number: 001-53145 Rev. *G Page 7 of 16
Figure 3. Data Transfer Sequence on the Serial Bus
Figure 4. Data Frame Architecture
Figure 5. Data Valid and Data Transition Periods
SCLK
START
Condition
SDA
STOP
Data may Address or
Acknowledge
Valid
be changed
Condition
SDA Write
Start Signal
Device
Address
7-bit
R/W
= 0
1 Bit
8-bit
Register
Address
Slave
1 Bit
ACK
Slave
1 Bit
ACK
8-bit
Register
Data
Stop Signal
Multiple
Contiguous
Registers
Slave
1 Bit
ACK
8-bit
Register
Data
(XXH) (XXH)
(XXH+1)
Slave
1 Bit
ACK
8-bit
Register
Data
(XXH+2)
Slave
1 Bit
ACK
8-bit
Register
Data
(FFH)
Slave
1 Bit
ACK
8-bit
Register
Data
(00H)
Slave
1 Bit
ACK
Slave
1 Bit
ACK
SDA Read
Start Signal
Device
Address
7-bit
R/W
= 1
1 Bit
8-bit
Register
Data
Slave
1 Bit
ACK
Slave
1 Bit
ACK
Stop Signal
SDA Read
Start Signal
Device
Address
7-bit
R/W
= 0
1 Bit
8-bit
Register
Address
Slave
1 Bit
ACK
Slave
1 Bit
ACK
7-bit
Device
Stop Signal
Multiple
Contiguous
Registers
Master
1 Bit
ACK
8-bit
Register
Data
Master
1 Bit
ACK
(XXH)
(XXH)
Master
1 Bit
ACK
8-bit
Register
Data
(XXH+1)
Master
1 Bit
ACK
8-bit
Register
Data
(FFH)
Master
1 Bit
ACK
8-bit
Register
Data
(00H)
Master
1 Bit
ACK
Master
1 Bit
ACK
Current
Address
Read
Address
+R/W=1
Repeated
Start bit
SDA
SCLK
Data Valid
Transition
to next Bit
CLK
LOW
CLK
HIGH
VIH
VIL
t
SU
t
DH
CY2XF23
Document Number: 001-53145 Rev. *G Page 8 of 16
Figure 6. Start and Stop Frame
Figure 7. Frame Format (Device Address, R/W
, Register Address, Register Data)
SDA
SCLK
START
Transition
to next Bit
STOP
SDA
SCLK
DA6 DA5 DA0 R/W ACK RA7 RA6 RA1 RA0 ACK STOP
START
ACK
D7 D6 D1 D0
+++
+
+
+
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
V
DD
Supply voltage –0.5 4.4 V
V
IN
[3]
Input voltage, DC Relative to V
SS
–0.5 V
DD
+ 0.5 V
T
S
Temperature, storage Non Operating –55 135 °C
T
J
Temperature, junction –40 135 °C
ESD
HBM
Electrostatic discharge (ESD) protection
human body model (HBM)
JEDEC Std 22-A114-B 2000 V
JA
[4]
Thermal resistance, junction to ambient 0 m/s airflow 64 °C/W
Operating Conditions
Parameter Description Min Typ Max Unit
V
DD
3.3-V supply voltage range 3.135 3.3 3.465 V
2.5-V supply voltage range 2.375 2.5 2.625 V
T
PU
Power-up time for V
DD
to reach minimum specified voltage (power ramp is
monotonic)
0.05 500 ms
T
A
Ambient temperature (commercial) 0 70 °C
Ambient temperature (industrial) –40 85 °C
Notes
3. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
4. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 × 114 × 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
CY2XF23
Document Number: 001-53145 Rev. *G Page 9 of 16
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
I
DD
[5]
Operating supply current V
DD
= 3.465 V, CLK = 150 MHz, output terminated 120 mA
V
DD
= 2.625 V, CLK = 150 MHz, output terminated 115 mA
V
OD
LVDS differential output
voltage
V
DD
= 3.3 V or 2.5 V, defined in Figure 8 on page 11
as terminated in Figure 13 on page 12.
247 454 mV
V
OD
Change in V
OD
between
complementary output states
V
DD
= 3.3 V or 2.5 V, defined in Figure 8 on page 11
as terminated in Figure 13 on page 12.
––50mV
V
OS
LVDS offset output voltage V
DD
= 3.3 V or 2.5 V, defined in Figure 9 on page 11
as terminated in Figure 13 on page 12.
1.125 1.375 V
V
OS
Change in V
OS
between
complementary output states
V
DD
= 3.3 V or 2.5 V, R
TERM
= 100 between CLK
and CLK#
––50mV
V
OLS
Output low voltage (SDA) I
OL
= 4 mA 0.1 × V
DD
V
V
IH
Input high voltage 0.7 × V
DD
–– V
V
IL
Input low voltage 0.3 × V
DD
V
I
IH0
Input high current (SDA) Input = V
DD
––115A
I
IH1
Input high current (SCLK) Input = V
DD
––10A
I
IL0
Input low current (SDA) Input = V
SS
–50 A
I
IL1
Input low current (SCLK) Input = V
SS
–20 A
C
IN0
[6]
Input capacitance (SDA) 15 pF
C
IN1
[6]
Input capacitance (SCLK) 4 pF
Notes
5. I
DD
includes ~4 mA of current that is dissipated externally in the output termination resistors.
6. Not 100% tested, guaranteed by design and characterization.

CY2XF23FLXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL HI PERFORMANCE LVDS OSCILLATOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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