XRD9827
25
Rev. 3.00
tdv tdv
AREA, LINEAR or B/W CCD -- AC Coupled
(CLAMP Enabled)
Pixel N-1 Pixel N Pixel N+1
CCD
Channel N
ADCCLK
tckpd
tap
tap
tckhw tcklw
CLAMP
tclpw
N-8
MSB
N-8
LSB
N-7
MSB
N-7
LSB
N-6
MSB
N-6
LSB
[5:0]
[11:6]
DB
Figure 15. Timing Diagram for Figure 14
Triple Channel CCD Application
Figure 16 is a block diagram for pixel-by-pixel applica-
tions with triple channel CCDs. During the optically
shielded section of a pixel, CLAMP must go high to
store the black reference on each capacitor to the input.
The gain and offset is automatically rotated to adjust for
each channel input. The MSBs are available on the
output bus on the falling edge of ADCCLK. The LSBs
are available on the rising edge of ADCCLK.
