R1LP0108E Series
R10DS0151EJ0100 Rev.1.00 Page 12 of 12
2013.6.21
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*2
V
CC
for data retention V
DR
2.0 - 5.5 V
Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
Data retention current I
CCDR
- 0.6
*1
2 A ~+25°C
Vcc=3.0V, Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
- - 3 A ~+40°C
- - 8 A ~+70°C
- - 10 A ~+85°C
Chip deselect time to data retention t
CDR
0 - - ns
See retention waveform.
Operation recovery time t
R
5 - - ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
Low Vcc Data Retention Timing Waveforms
CS1#
Vcc
(1) CS1# Controlled
t
CDR
t
R
4.5V 4.5V
2.2V 2.2V
DR
CS1# ≥
cc - 0.2V
CS2
Vcc
(2) CS2 Controlled
t
CDR
t
R
4.5V 4.5V
0.2V 0.2V
DR
0V ≤ CS2 ≤ 0.2V
