932S431AGLFT Datasheet 932S431AGLF, 932S431AGLFT | P19-P21

Integrated

Circuit

Systems, Inc.

ICS932S431A

Datasheet

1426A—11/12/09

PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.

When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is

de-asserted.

PD, Power Down

DPUPC#UPCCRS#CRSICP/FICPBSUFERetoN

0lamroNlamroNlamroNlamroNzHM33zHM84zHM813.411

1ro2*ferI

taolF

taolF2*ferI

taolFro

taolFwoLwo

LwoL1

Notes:

1. Refer to SMBus Byte 4 for additional information.

PD should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held

low on their next high to low transition.

All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register

determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.

When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x

Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.

See SMBus Bytes 4 and 5 for additional information.

PD Assertion

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC#, 100MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

Integrated

Circuit

Systems, Inc.

ICS932S431A

Datasheet

1426A—11/12/09

The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive

mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of

200mV in less than 300µs of PD deassertion.

PD De-assertion

Tstable

<1.8mS

Tdrive_PwrDwn#

<300µS, >200mV

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC# 100MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

Test Clarification Table

Comments

FS_C/TEST

_SEL

HW PIN

FS_B/TEST

_MODE

HW PIN

TEST

ENTRY

BIT

B6b6

REF/N or

HI-Z

B6b7 OUTPUT

0 X 0 X NORMAL

10X0HI-Z

10X1REF/N

11X0REF/N

11X1REF/N

0X10HI-Z

0X11REF/N

B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)

B6b7: 1= REF/N, Default = 0 (HI-Z)

HW S

Power-up w/ TEST_SEL = 1 to enter test mode

Cycle power to disable test mode

FS_C./TEST_SEL -->3-level latched input

If power-up w/ V>2.0V (-0.3V) then use TEST_SEL

If power-up w/ V<2.0V (-0.3V) then use FS_C

FS_B/TEST_MODE -->low Vth input

TEST_MODE is a real time input

If TEST_SEL HW pin is 0 during power-up,

test mode can be invoked through B6b6.

If test mode is invoked by B6b6, only B6b7

is used to select HI-Z or REF/N

FS_B/TEST_Mode pin is not used.

Cycle power to disable test mode, one shot control

Integrated

Circuit

Systems, Inc.

ICS932S431A

Datasheet

1426A—11/12/09

MIN MAX MIN MAX

A -- 1.20 -- .047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.17 0.27 .007 .011

c 0.09 0.20 .0035 .008

E1 6.00 6.20 .236 .244

L 0.45 0.75 .018 .030

0° 8° 0° 8°

aaa -- 0.10 -- .004

VARIATIONS

MIN MAX MIN MAX

56 13.90 14.10 .547 .555

10-0039

D mm. D (inch)

Reference Doc.: JEDEC Publication 95, MO-153

0.50 BASIC 0.020 BASIC

SEE VARIATIONS SEE VARIATIONS

8.10 BASIC 0.319 BASIC

6.10 mm. Body, 0.50 mm. Pitch TSSOP

(240 mil) (20 mil)

SYMBOL

In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

INDEX

AREA

INDEX

AREA

1 2

SEATING

PLANE

SEATING

PLANE

-C-

- C -

aaa

Ordering Information

Part / Order Number Shipping Packaging Package Temperature

932S431AGLF Tubes 56-pin TSSOP 0 to +70°C

932S431AGLFT Tape and Reel 56-pin TSSOP 0 to +70°C

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

"A" denotes the revision designator (will not correlate to datasheet revision).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

932S431AGLFT

Mfr. #:

Buy 932S431AGLFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK

Lifecycle:

New from this manufacturer.

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932S431AGLFT

932S431AGLFT

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