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932S431AGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
4
Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
1426A—11/12/09
ICS932S431A is a main clock synthesizer for CK410B-generation Intel server platforms. ICS932S431A is driven with a
14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100. The 48 MHz USB clock is an exact
48.000 MHz clock. The ICS932S431A generates all other clocks with less the +/- 300 ppm error.
General Description
Block Diagram
Power Groups
CPU PLL
CONTROL
LOGIC
XTAL
OSC.
CPUCLK(3:0)
FIXED PLL
48MHz
DIVIDER
DIVIDERS
REF(1:0)
SRCCLK(4:0)
S DATA
SCLK
X1
X2
IREF
FS(C:A)
VTT_PWRGD#/PD
SRC/PCI
PLL
DIVIDERS
TEST_SEL
PCICLK(3:0), PCICLK_F(2:0)
VDD GND
53 50 Xtal, Ref
1,8 2,7 PCICLK outputs
15,25,28 20 SRCCLK outputs
35 34 Master clock, CPU Analog
12 14 48MHz, PLL_48
47,44,38 41 CPUCLK clocks
Description
Pin Number
5
Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
1426A—11/12/09
Absolute Maximum Rating
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage VDD_A
-
V
DD
+ 0.5V V
1
3.3V Logic Input Supply
Voltage
VDD_In
-
GND - 0.5 V
DD
+ 0.5V V
1
Storage Temperature Ts
-
-65 150
°
C
1
Ambient Operatin
g
Tem
p
Tambient
-
0
7
0
°C
1
Case Temperature Tcase
-
115 °C
1
Input ESD protection HBM ESD prot
-
2000 V
1
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETE
R
SYMBO
L
CONDITIONS* MIN TYP MAX UNITS Notes
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA 1
Low Threshold Input-
Hi
h Volta
e
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Volta
g
e
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V 1
Operating Supply Current I
DD3.3OP
Full Active, C
L
= Full load; 350 mA 1
all diff pairs driven 70 mA 1
all differential pairs tri-stated 12 mA 1
Input Frequency F
i
V
DD
= 3.3 V 14.31818 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OU
T
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization T
STAB
From VDD Power-Up or de-
assertion of PD to 1st clock
1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdrive_PD
CPU output enable after
PD de-assertion
300 us 1
Tfall_PD PD fall time of 5 ns 1
Trise_PD PD rise time of 5 ns 1
SMBus Voltage V
DD
2.7 5.5 V 1
Low-level Output Voltage V
OL
@ I
PULLUP
0.4 V 1
Current sinking at
V
OL
= 0.4 V
I
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
T
RI 2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI 2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input Low Current
Powerdown Current I
DD3.3PD
Input Capacitance
6
Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
1426A—11/12/09
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
PARAMETE
R
SYMBO
L
CONDITIONS* MIN TYP MAX UNITS Notes
Current Source Output
Impedance
Zo VO = Vx 3000
Ω
1
Voltage High VHigh 660 850 mV 1,3
Volta
g
e Lo
w
VLo
w
-150 150 mV 1,
3
Max Volta
g
eVovs 1150mV1
Min Volta
g
e Vuds -300 mV 1
Crossin
g
Volta
g
e (abs) Vx(abs) 250 550 mV 1
Crossing Voltage (var) d-Vx
Variation of crossing over all
edges
140 mV 1
Rise Time tr VOL = 0.175V, VOH = 0.525V 175 525 ps 1
Fall Time tf VOH = 0.525V VOL = 0.175V 175 525 ps 1
Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1
Fall Time Variation d-tf VOH = 0.525V VOL = 0.175V 125 ps 1
Long Term Jitter t
jLT
Measurement from differential
wavefrom @ 10 us
0300500ps1
Duty Cycle dt3
Measurement from differential
wavefrom
45 55 % 1
Skew tsk3 VT = 50% 250 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
Measurement from differential
wavefrom
125 ps 1
*T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω
, I
REF
= 475
Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
Statistical measurement on
sin
g
le ended si
g
nal
Measurement on single ended
si
g
nal usin
g
absolute value.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
Zo VO = Vx 3000
Ω
1
Voltage High VHigh 660 850 mV 1,3
Voltage Low VLow -150 150 mV 1,3
Max Voltage Vovs 1150 mV 1
Min Voltage Vuds -300 mV 1
Crossing Voltage (abs) Vx(abs) 250 550 mV 1
Crossing Voltage (var) d-Vx
Variation of crossing over all
edges
140 mV 1
Rise Time tr V
OL
= 0.175V, V
OH
= 0.525V 175 525 ps 1
Fall Time tf V
OL
= 0.175V, V
OH
= 0.525V 175 525 ps 1
Rise Time Variation d-tr V
OL
= 0.175V, V
OH
= 0.525V 125 ps 1
Fall Time Variation d-tf V
OL
= 0.175V, V
OH
= 0.525V 125 ps 1
Duty Cycle dt3
Measurement from differential
wavefrom
45 55 % 1
Skew tsk3
across all CPU outputs,
VT = 50%
50 ps 1
Jitter, Cycle to cycle t
jcyc-cyc
Measurement from differential
wavefrom
50 ps 1
*T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω
, I
REF
= 475
Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
RE
F
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
Statistical measurement on
single ended signal
Measurement on single ended
signal using absolute value.
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932S431AGLFT

Mfr. #:
Buy 932S431AGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
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