XC18V00 Series In-System Programmable Configuration PROMs
6 www.xilinx.com DS026 (v3.9) November 18, 2002
1-800-255-7778 Product Specification
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Capacity
In-System Programming
In-System Programmable PROMs can be programmed indi-
vidually, or two or more can be daisy-chained together and
programmed in-system via the standard 4-pin JTAG proto-
col as shown in Figure 2. In-system programming offers
quick and efficient design iterations and eliminates unnec-
essary package handling or socketing of devices. The Xilinx
development system provides the programming data
sequence using either Xilinx iMPACT software and a
download cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format and with
automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
OE/RESET
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130 or a third-party device programmer. This
provides the added flexibility of using pre-programmed
devices with an in-system programmable option for future
enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorpo-
rate advanced data security features to fully protect the pro-
gramming data against unauthorized reading via JTAG.
Table 3 shows the security setting available.
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 3 : Data Security Options
XCV1600E 8,308,992 2 of XC18V04
XCV2000E 10,159,648 3 of XC18V04
XCV2600E 12,922,336 4 of XC18V04
XCV3200E 16,283,712 4 of XC18V04
XC2S15 197,696 XC18V256
XC2S30 336,768 XC18V512
XC2S50 559,200 XC18V01
XC2S100 781,216 XC18V01
XC2S150 1,040,096 XC18V01
XC2S200 1,335,840 XC18V02
XC2S50E 630,048 XC18V01
XC2S100E 863,840 XC18V01
XC2S150E 1,134,496 XC18V02
XC2S200E 1,442,016 XC18V02
XC2S300E 1,875,648 XC18V02
XC2S400E 2,693,440 XC18V04
XC2S600E 3,961,632 XC18V04
Devices Configuration Bits
XC18V04 4,194,304
XC18V02 2,097,152
XC18V01 1,048,576
XC18V512 524,288
XC18V256 262,144
Table 2: Xilinx FPGAs and Compatible PROMs
Device
Configuration
Bits
XC18V00
Solution
Default = Reset Set
Read Allowed
Program/Erase Allowed
Verify A llowed
Read Inhibited via JTAG
Program/Erase Allowed
Verify Inhibited
