ATF-521P8-TR1 Datasheet ATF-521P8-TR1, ATF-521P8-BLK, ATF-521P8-TR2 | P16-P18

Figure 8. Passive Biasing.

Active Bias

[2]

Due to very high DC power dissipation and small

package constraints, it is recommended that ATF‑521P8

use active biasing. The main advantage of an active

biasing scheme is the ability to hold the drain to source

current constant over a wide range of temperature

variations.

A very inexpensive method of accomplishing this

is to use two PNP bipolar transistors arranged in a

current mirror conguration as shown in Figure 9. Due

to resistors R1 and R3, this circuit is not acting as a

true current mirror, but if the voltage drop across R1

and R3 is kept identical then it still displays some of

the more useful characteristics of a current mirror. For

example, transistor Q1 is congured with its base and

collector tied together. This acts as a simple PN junction,

which helps temperature compensate the Emitter‑Base

junction of Q2.

To calculate the values of R1, R2, R3, and R4 the

following parameters must be know or chosen rst:

is the device drain‑to‑source current;

is the Reference current for active bias;

is the power supply voltage available;

is the device drain‑to‑source voltage;

is the typical gate bias;

be1

is the typical Base‑Emitter turn on voltage for Q1 &

Q2;

Therefore, resistor R3, which sets the desired device

drain current, is calculated as follows:

R3 =

– V

(4)

+ I

where,

is chosen for stability to be 10 times the typical gate

current and also equal to the reference current I

The next three equations are used to calculate the

rest of the biasing resistors for Figure 9. Note that the

voltage drop across R1 must be set equal to the voltage

drop across R3, but with a current of I

R1 =

– V

(5)

R2 sets the bias current through Q1.

R2 =

– V

be1

(6)

R4 sets the gate voltage for ATF‑521P8.

R4 =

(7)

C 2

Thus, by forcing the emitter voltage (V

) of transistor

Q1 equal to V

, this circuit regulates the drain current

similar to a current mirror. As long as Q2 operates in the

forward active mode, this holds true. In other words, the

Collector‑Base junction of Q2 must be kept reversed

biased.

Vdd

ATF-521P8

2PL

Figure 9. Active Bias Circuit.

INPUT

OUTPUT

Vdd

PCB Layout

A recommended PCB pad layout for the Leadless Plastic

Chip Carrier (LPCC) package used by the ATF‑521P8 is

shown in Figure 10. This layout provides plenty of plated

through hole vias for good thermal and RF grounding. It

also provides a good transition from microstrip to the

device package. For more detailed dimensions refer to

Section 9 of the data sheet.

This simplies RF grounding by reducing the amount

of inductance from the source to ground. It is also

recommended to ground pins 1 and 4 since they are

also connected to the device source. Pins 3, 5, 6, and 8

are not connected, but may be used to help dissipate

heat from the package or for better alignment when

soldering the device.

This three‑layer board (Figure 12) contains a 10‑mil layer

and a 52‑mil layer separated by a ground plane. The rst

layer is Getek RG200D material with dielectric constant

of 3.8. The second layer is for mechanical rigidity and

consists of FR4 with dielectric constant of 4.2.

High Linearity Tx Driver

The need for higher data rates and increased voice

capacity gave rise to a new third generation standard

know as Wideband CDMA or UMTS. This new standard

requires higher performance from radio components

such as higher dynamic range and better linearity. For

example, a WCDMA waveform has a very high peak to

average ratio which forces ampliers in a transmit chain

to have very good Adjacent Channel Leakage power

Ratio or ACLR, or else operate in a backed o mode.

If the amplier is not backed o then the waveform is

compressed and the signal becomes very nonlinear.

This application example presents a highly linear

transmit drive for use in the 2.14GHz frequency range.

Using the RF matching techniques described earlier,

ATF‑521P8 is matched to the following input and output

impedances:

Figure 12. ATF-521P8 demoboard.

Pin 8

Source

(Thermal/RF Gnd)

Pin 7 (Drain)

Pin 6

Pin 5

Pin 1 (Source)

Pin 2 (Gate)

Pin 3

Pin 4 (Source)

Bottom View

BCV62B

short

Figure 10. Microstripline Layout.

RF Grounding

Unlike SOT packages, ATF‑521P8 is housed in a leadless

package with the die mounted directly to the lead

frame or the belly of the package shown in Figure 11.

Figure 11. LPCC Package for ATF-521P8.

Figure 13. ATF-521P8 Matching.

As described previously the input impedance must

be matched to S11* in order to guarantee return loss

greater than 10 dB. A high pass network is chosen for

this match. The output is matched to Γ

with another

high pass network. The next step is to choose the

proper DC biasing conditions. From the data sheet,

ATF‑521P8 produces good linearity at a drain current

of 200mA and a drain to source voltage of 4.5V. Thus to

construct the active bias circuit described, the following

parameters are given:

Ids = 200 mA

= 10 mA

= 5 V

= 4.5V

= 0.62V

be1

= 0.65 V

Using equations 4, 5, 6, and 7, the biasing resistor values

are calculated in column 2 of table 1, and the actual

values used are listed in column 3.

Table 1. Resistors for Active Bias.

Resistor Calculated Actual

R1 50Ω 49.9Ω

R2 385Ω 383Ω

R3 2.38Ω 2.37Ω

R4 62Ω 61.9Ω

The entire circuit schematic for a 2.14 GHz Tx driver

amplier is shown below in Figure 14. Capacitors C4,

C5, and C6 are added as a low frequency bypass. These

terminate second order harmonics and help improve

linearity. Resistors R5 and R6 also help terminate low

frequencies, and can prevent resonant frequencies

between the two bypass capacitors.

Performance of ATF-521P8 at 2140 MHz

ATF‑521P8 delivers excellent performance in the

WCDMA frequency band. With a drain‑to‑source voltage

of 4.5V and a drain current of 200 mA, this device has

16.5 dB of gain and 1.55 dB of noise gure as show in

Figure 15.

Figure 14. 2140 MHz Schematic.

C1=1.2pF

L4=3.9nH

L1=1.0nH

L2=12nH

L3=39nH

R6=1.2Ω

R5=10Ω

R3=2.37Ω

R4=61.9Ω

C4=1µF

C3=4.7pF

C8=1.5pF

C7=150pF

C5=1µF

C6=.1µF

IC2

C2=1.5nH

R1=49.9Ω

R2=383Ω

be1

+5V

ATF-521P8

2PL

Input

Match

Output

Match

2PL

50 Ohm

S11* = 0.89∠ -169 Γ

= 0.53∠ -176

50 Ohm

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

ATF-521P8-TR1

Mfr. #:

Buy ATF-521P8-TR1

Manufacturer:

Broadcom / Avago

Description:

RF JFET Transistors Transistor GaAs High Linearity

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ATF-521P8-TR1

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