AD7390ARZ-REEL7

REV. A
AD7390/AD7391
–4–
PIN DESCRIPTIONS
Pin No. Name Function
1 LD Load Strobe. Transfers shift register
data to DAC register while active low.
See truth table for operation.
2 CLK Clock Input. Positive edge clocks data
into shift register.
3 SDI Serial Data Input. Data loads directly
into the shift register.
4 CLR Resets DAC register to zero condition.
Active low input.
5 GND Analog and Digital Ground.
6V
OUT
DAC Voltage Output. Full-scale output
1 LSB less than reference input voltage REF.
7V
DD
Positive Power Supply Input. Specified
range of operation 2.7 V to 5.5 V.
8V
REF
DAC Reference Input Pin. Establishes
DAC full-scale voltage.
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, 8 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V
DD
0.3 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .0.3 V, 8 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . . 0.3 V, V
DD
0.3 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (T
J MAX
T
A
)/θ
JA
Thermal Resistance θ
JA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . . 240°C/W
Maximum Junction Temperature (T
J MAX
) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . 40°C to 85°C
AD7391AR . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C
Storage Temperature Range . . . . . . . . . . . 65°C to 150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
specification is not implied. Exposure to the above maximum rating conditions for
extended periods may affect device reliability.
DAC
REGISTER
RESET
LOAD
CLK
12-BIT AD7390*
SHIFT REGISTER
D
CLR
LD
CLK
SDI
12
*AD7391 HAS A 10-BIT SHIFT REGISTER
Figure 3. Digital Control Logic
PIN CONFIGURATIONS
TOP VIEW
(Not to
Scale)
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
LD
CLK
CLR
SDI
GND
V
REF
V
DD
V
OUT
TSSOP-8
SO-8
P-DIP-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7390/AD7391 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
1
Temperature Package Package Top Number of Devices
Model Resolution Range Description Option Mark
2
Per Container
AD7390AN 12 40°C to 85°C 8-Lead P-DIP N-8 AD7390
2
50
AD7390AR 12 40°C to 85°C 8-Lead SOIC SO-8 AD7390
3
196
AD7390AR-REEL7 12 40°C to 85°C 8-Lead SOIC SO-8 AD7390
3
1000
AD7391AN 10 40°C to 85°C 8-Lead P-DIP N-8 AD7391
2
50
AD7391AR 10 40°C to 125°C 8-Lead SOIC SO-8 AD7391
3
196
AD7391SR 10 55°C to 125°C 8-Lead SOIC SO-8 AD7391
3
39
AD7391ARU-REEL 10 40°C to 85°C TSSOP-8 RU-8 AD7391A
4
2500
NOTES
1
The AD7390 contains 588 transistors. The die size measures 70 mm 68 mm.
2
Line 1 contains ADI logo symbol and part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number.
3
Line 1 contains part number. Line 2 contains grade and date code YWW. Line 3 contains the letter G plus the 4-digit lot number and the ADI logo symbol.
4
Line 1 contains the date code YWW. Line 2 contains the 4-digit part number plus grade.
REV. A
AD7390/AD7391
–5–
DAC REGISTER LOAD
CLK
CLR
LD
CLK
SDI
AD7391AD7390
t
LD1
D11
t
LD1
D10 D9 D7 D5 D4 D3 D2 D1 D0
t
LD2
t
DS
t
DH
t
CL
t
CH
t
LDW
t
S
t
CLRW
t
S
0.1% FS
ERROR BAND
SDI
LD
FS
ZS
V
OUT
Figure 4. Timing Diagram
Table I. Control-Logic Truth Table
CLK CLR LD Serial Shift Register Function DAC Register Function
H H Shift-Register-Data Advanced One-Bit Latched
X H L Disables Updated with Current Shift Register Contents
X L X No Effect Loaded with all Zeros
X H No Effect Latched with all Zeros
X L Disabled Previous SR Contents Loaded (Avoid usage of CLR
when LD is logic low, since SR data could be corrupted
if a clock edge takes place, while CLR returns high.)
= Positive logic transition.
X = Dont care.
Table II. AD7390 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7390 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table III. AD7391 Serial Input Register Data Format, Data is Loaded in the MSB-First Format
MSB LSB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7391 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
REV. A
AD7390/AD7391Typical Performance Characteristics
–6–
TOTAL UNADJUSTED ERROR LSB
FREQUENCY
25
0
5.0
10
5
20
15
5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0
SS = 100 UNITS
T
A
= 25C
V
DD
= 2.7V
V
REF
= 2.5V
TPC 1. AD7390 Total Unadjusted
Error Histogram
FREQUENCY Hz
OUTPUT VOLTAGE NOISE V
Hz
10
8
0
1 10 100k
100 1k 10k
6
4
2
12
14
16
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25C
TPC 4. AD7390 Voltage Noise
Density vs. Frequency
TEMPERATURE C
SUPPLY CURRENT A
100
20
55 35 125
15 5 25 65 85 10545
90
60
50
40
30
80
70
SAMPLE SIZE = 300 UNITS
V
DD
= 5.0V, V
LOGIC
= 0V
V
DD
= 3.0V, V
LOGIC
= 0V
V
DD
= 3.6V, V
LOGIC
= 2.4V
TPC 7. AD7390 Supply Current
vs. Temperature
TOTAL UNADJUSTED ERROR LSB
FREQUENCY
100
0
10
40
20
80
60
3.3 3.3 10 16 23 30 36 43 50
SS = 300 UNITS
T
A
= 25C
V
DD
= 2.7V
V
REF
= 2.5V
90
70
50
30
10
TPC 2. AD7391 Total Unadjusted
Error Histogram
V
IN
V
0.0 0.5 3.0
1.0 1.5 2.0 2.5
SUPPLY CURRENT A
100
95
50
70
65
60
55
90
75
80
85
V
LOGIC
FROM
3.0V TO 0V
V
LOGIC
FROM
0V TO 3.0V
T
A
= 25C
V
DD
= 3.0V
TPC 5. AD7390 Supply Current vs.
Logic Input Voltage
CLOCK FREQUENCY Hz
SUPPLY CURRENT A
1000
800
0
1k 10k 10M
100k 1M
600
400
200
a. V
DD
= 5.5V, CODE = 155
H
b. V
DD
= 5.5V, CODE = 3FF
H
c. V
DD
= 2.7V, CODE = 155
H
d
. V
DD
= 2.7V, CODE = 355
H
a
b
c
d
V
LOGIC
= 0V TO V
DD
TO 0V
V
REF
= 2.5V
T
A
= 25C
TPC 8. AD7391 Supply Current
vs. Clock Frequency
FULL-SCALE TEMPCO ppm/ C
FREQUENCY
0
33
12
6
24
18
30 26 23 20 16 13 10 6 3
30
0
SS = 100 UNITS
T
A
= 40C TO +85C
V
DD
= 2.7V
V
REF
= 2.5V
TPC 3. AD7391 Full-Scale Output
Tempco Histogram
SUPPLY VOLTAGE V
12 7
34 56
THRESHOLD VOLTAGE V
5.0
4.5
0.0
2.0
1.5
1.0
0.5
4.0
2.5
3.0
3.5
V
LOGIC
FROM
HIGH TO LOW
V
LOGIC
FROM
LOW TO HIGH
CODE = FFF
H
V
REF
= 2V
RS LOGIC VOLTAGE
VARIED
TPC 6. AD7390 Logic Threshold
vs. Supply Voltage
FREQUENCY Hz
PSRR dB
60
50
0
10 100 10k
1k
30
20
10
40
V
DD
= 3V 5%
V
DD
= 5V 5%
T
A
= 25C
TPC 9. Power Supply Rejection
vs. Frequency

AD7390ARZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 12B +3V MICROPWR
Lifecycle:
New from this manufacturer.
Delivery:
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